From patchwork Wed Apr 21 15:34:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12216375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5592BC43460 for ; Wed, 21 Apr 2021 15:34:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EEE1C61428 for ; Wed, 21 Apr 2021 15:34:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EEE1C61428 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C7C516E9B5; Wed, 21 Apr 2021 15:34:21 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7AD0F6E9AE; Wed, 21 Apr 2021 15:34:20 +0000 (UTC) IronPort-SDR: CSvwCamzWT+U3Gtl/ANhNM5tx7uzuTZbpUmZkNu4PLCJryFJGFS0K1Zw/toS1hZAybPKtvqu90 xYhsyb6Rtttg== X-IronPort-AV: E=McAfee;i="6200,9189,9961"; a="182848733" X-IronPort-AV: E=Sophos;i="5.82,240,1613462400"; d="scan'208";a="182848733" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2021 08:34:19 -0700 IronPort-SDR: 3yUj4oXM5bOHNjqfuAr+NwGStlP8lhWuZZKaRxmLlolsu4hnSVwDCHIbSRGCAowxKaAGeoDdg0 OTwgYybP9AVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,240,1613462400"; d="scan'208";a="524331344" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga001.fm.intel.com with SMTP; 21 Apr 2021 08:34:17 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 21 Apr 2021 18:34:16 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection Date: Wed, 21 Apr 2021 18:34:01 +0300 Message-Id: <20210421153401.13847-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210421153401.13847-1-ville.syrjala@linux.intel.com> References: <20210421153401.13847-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, Chris Wilson Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Ville Syrjälä Currently we try to detect a symmetric memory configurations using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is either only set on a very specific subset of machines or it just does not exist (it's not mentioned in any public chipset datasheets I've found). As it happens my CL/CTG machines never set said bit, even if I populate the channels with identical sticks. So let's do the L-shaped memory detection the same way as the desktop variants, ie. just look at the DRAM rank boundary registers to see if both channels have an identical size. With this my CL/CTG no longer claim L-shaped memory when I use identical sticks. Also tested with non-matching sticks just to make sure the L-shaped memory is still properly detected. And for completeness let's update the debugfs code to dump the correct set of registers on each platform. Cc: Chris Wilson Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ++++++++------- drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 3 files changed, 24 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index 0fa6c38893f7..754f20768de5 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; swizzle_y = I915_BIT_6_SWIZZLE_9_17; } - break; - } - /* check for L-shaped memory aka modified enhanced addressing */ - if (IS_GEN(i915, 4) && - !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) { - swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; - swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; + /* check for L-shaped memory aka modified enhanced addressing */ + if (IS_GEN(i915, 4) && + intel_uncore_read16(uncore, C0DRB3_CL) != + intel_uncore_read16(uncore, C1DRB3_CL)) { + swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; + swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; + } + break; } if (dcc == 0xffffffff) { diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8dd374691102..6de11ffcde38 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void *data) intel_uncore_read(uncore, DCC)); seq_printf(m, "DDC2 = 0x%08x\n", intel_uncore_read(uncore, DCC2)); - seq_printf(m, "C0DRB3 = 0x%04x\n", - intel_uncore_read16(uncore, C0DRB3_BW)); - seq_printf(m, "C1DRB3 = 0x%04x\n", - intel_uncore_read16(uncore, C1DRB3_BW)); + + if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) { + seq_printf(m, "C0DRB3 = 0x%04x\n", + intel_uncore_read16(uncore, C0DRB3_BW)); + seq_printf(m, "C1DRB3 = 0x%04x\n", + intel_uncore_read16(uncore, C1DRB3_BW)); + } else if (IS_GEN(dev_priv, 4)) { + seq_printf(m, "C0DRB3 = 0x%04x\n", + intel_uncore_read16(uncore, C0DRB3_CL)); + seq_printf(m, "C1DRB3 = 0x%04x\n", + intel_uncore_read16(uncore, C1DRB3_CL)); + } } else if (INTEL_GEN(dev_priv) >= 6) { seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", intel_uncore_read(uncore, MAD_DIMM_C0)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0587b2455ea1..055c258179a1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3790,6 +3790,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206) #define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606) +/* 965gm,ctg DRAM channel configuration */ +#define C0DRB3_CL _MMIO(MCHBAR_MIRROR_BASE + 0x1206) +#define C1DRB3_CL _MMIO(MCHBAR_MIRROR_BASE + 0x1306) + /* snb MCH registers for reading the DRAM channel configuration */ #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)