| Message ID | 20210729170737.21424-2-jason-jh.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Mediatek Soc DRM (vdosys0) support for mt8195 | expand |
Hi, Jason: jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月30日 週五 上午1:07寫道： > > Add display node for vdosys0. > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > --- > This patch is based on [1][2][3][4] > > [1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile > - https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/ > [2]arm64: dts: mt8195: add IOMMU and smi nodes > - https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/ > [3]arm64: dts: mt8195: add gce node > - https://patchwork.kernel.org/project/linux-mediatek/patch/20210705053429.4380-4-jason-jh.lin@mediatek.com/ > [4]add mt8195 SoC DRM binding > - https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597 > --- > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 112 +++++++++++++++++++++++ > 1 file changed, 112 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index 04d3e95175fa..4fa47cb2bede 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -1155,9 +1155,121 @@ > #clock-cells = <1>; > }; > [snip] > + > + merge0: disp_vpp_merge0@1c014000 { > + compatible = "mediatek,mt8195-disp-merge"; > + reg = <0 0x1c014000 0 0x1000>; > + interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; Why this merge has no async clock? Regards, Chun-Kuang. > + mediatek,gce-client-reg = > + <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>; > + }; > +
Hi CK, On Sun, 2021-08-01 at 08:36 +0800, Chun-Kuang Hu wrote: > Hi, Jason: > > jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月30日 週五 上午1:07寫道： > > > > Add display node for vdosys0. > > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > > --- > > This patch is based on [1][2][3][4] > > > > [1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and > > Makefile > > - > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/__;!!CTRNKA9wMg0ARbw!3bjfjGf2GYJ5FQ5EWsjG9yPGwf6uVMv8dDyXLY2Tlq_sTczeIJkEDTWVt1dxp4b7tojj$ > > > > [2]arm64: dts: mt8195: add IOMMU and smi nodes > > - > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/__;!!CTRNKA9wMg0ARbw!3bjfjGf2GYJ5FQ5EWsjG9yPGwf6uVMv8dDyXLY2Tlq_sTczeIJkEDTWVt1dxp0sfXPc-$ > > > > [3]arm64: dts: mt8195: add gce node > > - > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210705053429.4380-4-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!3bjfjGf2GYJ5FQ5EWsjG9yPGwf6uVMv8dDyXLY2Tlq_sTczeIJkEDTWVt1dxp5uw6cqB$ > > > > [4]add mt8195 SoC DRM binding > > - > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597__;!!CTRNKA9wMg0ARbw!3bjfjGf2GYJ5FQ5EWsjG9yPGwf6uVMv8dDyXLY2Tlq_sTczeIJkEDTWVt1dxp0qn1imR$ > > > > --- > > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 112 > > +++++++++++++++++++++++ > > 1 file changed, 112 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > index 04d3e95175fa..4fa47cb2bede 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > @@ -1155,9 +1155,121 @@ > > #clock-cells = <1>; > > }; > > > > [snip] > > > + > > + merge0: disp_vpp_merge0@1c014000 { > > + compatible = "mediatek,mt8195-disp-merge"; > > + reg = <0 0x1c014000 0 0x1000>; > > + interrupts = <GIC_SPI 656 > > IRQ_TYPE_LEVEL_HIGH 0>; > > + power-domains = <&spm > > MT8195_POWER_DOMAIN_VDOSYS0>; > > + clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; > > Why this merge has no async clock? > > Regards, > Chun-Kuang. > Only the MERGE linked to the display function block that is cross vdosys0 to vdosys1 need to add async clock. I'll add this description into this patch [1] [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210729154912.20051-4-jason-jh.lin@mediatek.com/ Regards, Jason-JH.Lin > > + mediatek,gce-client-reg = > > + <&gce1 SUBSYS_1c01XXXX 0x4000 > > 0x1000>; > > + }; > > +
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 04d3e95175fa..4fa47cb2bede 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1155,9 +1155,121 @@ #clock-cells = <1>; }; + ovl0: disp_ovl@1c000000 { + compatible = "mediatek,mt8195-disp-ovl", + "mediatek,mt8183-disp-ovl"; + reg = <0 0x1c000000 0 0x1000>; + interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; + mediatek,gce-client-reg = + <&gce1 SUBSYS_1c00XXXX 0x0000 0x1000>; + }; + + rdma0: disp_rdma@1c002000 { + compatible = "mediatek,mt8195-disp-rdma"; + reg = <0 0x1c002000 0 0x1000>; + interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; + mediatek,gce-client-reg = + <&gce1 SUBSYS_1c00XXXX 0x2000 0x1000>; + }; + + color0: disp_color@1c003000 { + compatible = "mediatek,mt8195-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1c003000 0 0x1000>; + interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; + mediatek,gce-client-reg = + <&gce1 SUBSYS_1c00XXXX 0x3000 0x1000>; + }; + + ccorr0: disp_ccorr@1c004000 { + compatible = "mediatek,mt8195-disp-ccorr", + "mediatek,mt8183-disp-ccorr"; + reg = <0 0x1c004000 0 0x1000>; + interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; + mediatek,gce-client-reg = + <&gce1 SUBSYS_1c00XXXX 0x4000 0x1000>; + }; + + aal0: disp_aal@1c005000 { + compatible = "mediatek,mt8195-disp-aal", + "mediatek,mt8173-disp-aal"; + reg = <0 0x1c005000 0 0x1000>; + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; + mediatek,gce-client-reg = + <&gce1 SUBSYS_1c00XXXX 0x5000 0x1000>; + }; + + gamma0: disp_gamma@1c006000 { + compatible = "mediatek,mt8195-disp-gamma", + "mediatek,mt8173-disp-gamma"; + reg = <0 0x1c006000 0 0x1000>; + interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; + mediatek,gce-client-reg = + <&gce1 SUBSYS_1c00XXXX 0x6000 0x1000>; + }; + + dither0: disp_dither@1c007000 { + compatible = "mediatek,mt8195-disp-dither", + "mediatek,mt8183-disp-dither"; + reg = <0 0x1c007000 0 0x1000>; + interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; + mediatek,gce-client-reg = + <&gce1 SUBSYS_1c00XXXX 0x7000 0x1000>; + }; + + dsc0: disp_dsc_wrap@1c009000 { + compatible = "mediatek,mt8195-disp-dsc"; + reg = <0 0x1c009000 0 0x1000>; + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; + mediatek,gce-client-reg = + <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>; + }; + + merge0: disp_vpp_merge0@1c014000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c014000 0 0x1000>; + interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; + mediatek,gce-client-reg = + <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>; + }; + + mutex: disp_mutex0@1c016000 { + compatible = "mediatek,mt8195-disp-mutex"; + reg = <0 0x1c016000 0 0x1000>; + reg-names = "vdo0_mutex"; + interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + clock-names = "vdo0_mutex"; + mediatek,gce-events = + <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; + }; + vdosys0: syscon@1c01a000 { compatible = "mediatek,mt8195-vdosys0", "syscon"; reg = <0 0x1c01a000 0 0x1000>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + mboxes = <&gce1 0 CMDQ_THR_PRIO_4>; #clock-cells = <1>; };
Add display node for vdosys0. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> --- This patch is based on [1][2][3][4] [1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile - https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/ [2]arm64: dts: mt8195: add IOMMU and smi nodes - https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/ [3]arm64: dts: mt8195: add gce node - https://patchwork.kernel.org/project/linux-mediatek/patch/20210705053429.4380-4-jason-jh.lin@mediatek.com/ [4]add mt8195 SoC DRM binding - https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597 --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 112 +++++++++++++++++++++++ 1 file changed, 112 insertions(+)