diff mbox series

[v2,3/5] drm: rcar-du: Fix DIDSR field name

Message ID 20210901234907.1608896-4-kieran.bingham@ideasonboard.com (mailing list archive)
State New, archived
Headers show
Series [v2,1/5] drm: rcar-du: Sort the DU outputs | expand

Commit Message

Kieran Bingham Sept. 1, 2021, 11:49 p.m. UTC
The DIDSR fields named LDCS were incorrectly defined as LCDS.
Both the Gen2 and Gen3 documentation refer to the fields as the "LVDS
Dot Clock Select".

Correct the definitions.

Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>

---
v2:
 - New patch

 drivers/gpu/drm/rcar-du/rcar_du_group.c | 4 ++--
 drivers/gpu/drm/rcar-du/rcar_du_regs.h  | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

Comments

Laurent Pinchart Sept. 22, 2021, 5:30 p.m. UTC | #1
Hi Kieran,

Thank you for the patch.

On Thu, Sep 02, 2021 at 12:49:05AM +0100, Kieran Bingham wrote:
> The DIDSR fields named LDCS were incorrectly defined as LCDS.
> Both the Gen2 and Gen3 documentation refer to the fields as the "LVDS
> Dot Clock Select".
> 
> Correct the definitions.
> 
> Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
> v2:
>  - New patch
> 
>  drivers/gpu/drm/rcar-du/rcar_du_group.c | 4 ++--
>  drivers/gpu/drm/rcar-du/rcar_du_regs.h  | 8 ++++----
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
> index 88a783ceb3e9..a984eef265d2 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
> @@ -122,10 +122,10 @@ static void rcar_du_group_setup_didsr(struct rcar_du_group *rgrp)
>  	didsr = DIDSR_CODE;
>  	for (i = 0; i < num_crtcs; ++i, ++rcrtc) {
>  		if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index))
> -			didsr |= DIDSR_LCDS_LVDS0(i)
> +			didsr |= DIDSR_LDCS_LVDS0(i)
>  			      |  DIDSR_PDCS_CLK(i, 0);
>  		else
> -			didsr |= DIDSR_LCDS_DCLKIN(i)
> +			didsr |= DIDSR_LDCS_DCLKIN(i)
>  			      |  DIDSR_PDCS_CLK(i, 0);
>  	}
>  
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
> index fb9964949368..fb7c467aa484 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
> @@ -257,10 +257,10 @@
>  
>  #define DIDSR			0x20028
>  #define DIDSR_CODE		(0x7790 << 16)
> -#define DIDSR_LCDS_DCLKIN(n)	(0 << (8 + (n) * 2))
> -#define DIDSR_LCDS_LVDS0(n)	(2 << (8 + (n) * 2))
> -#define DIDSR_LCDS_LVDS1(n)	(3 << (8 + (n) * 2))
> -#define DIDSR_LCDS_MASK(n)	(3 << (8 + (n) * 2))
> +#define DIDSR_LDCS_DCLKIN(n)	(0 << (8 + (n) * 2))
> +#define DIDSR_LDCS_LVDS0(n)	(2 << (8 + (n) * 2))
> +#define DIDSR_LDCS_LVDS1(n)	(3 << (8 + (n) * 2))
> +#define DIDSR_LDCS_MASK(n)	(3 << (8 + (n) * 2))
>  #define DIDSR_PDCS_CLK(n, clk)	(clk << ((n) * 2))
>  #define DIDSR_PDCS_MASK(n)	(3 << ((n) * 2))
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index 88a783ceb3e9..a984eef265d2 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -122,10 +122,10 @@  static void rcar_du_group_setup_didsr(struct rcar_du_group *rgrp)
 	didsr = DIDSR_CODE;
 	for (i = 0; i < num_crtcs; ++i, ++rcrtc) {
 		if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index))
-			didsr |= DIDSR_LCDS_LVDS0(i)
+			didsr |= DIDSR_LDCS_LVDS0(i)
 			      |  DIDSR_PDCS_CLK(i, 0);
 		else
-			didsr |= DIDSR_LCDS_DCLKIN(i)
+			didsr |= DIDSR_LDCS_DCLKIN(i)
 			      |  DIDSR_PDCS_CLK(i, 0);
 	}
 
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
index fb9964949368..fb7c467aa484 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
@@ -257,10 +257,10 @@ 
 
 #define DIDSR			0x20028
 #define DIDSR_CODE		(0x7790 << 16)
-#define DIDSR_LCDS_DCLKIN(n)	(0 << (8 + (n) * 2))
-#define DIDSR_LCDS_LVDS0(n)	(2 << (8 + (n) * 2))
-#define DIDSR_LCDS_LVDS1(n)	(3 << (8 + (n) * 2))
-#define DIDSR_LCDS_MASK(n)	(3 << (8 + (n) * 2))
+#define DIDSR_LDCS_DCLKIN(n)	(0 << (8 + (n) * 2))
+#define DIDSR_LDCS_LVDS0(n)	(2 << (8 + (n) * 2))
+#define DIDSR_LDCS_LVDS1(n)	(3 << (8 + (n) * 2))
+#define DIDSR_LDCS_MASK(n)	(3 << (8 + (n) * 2))
 #define DIDSR_PDCS_CLK(n, clk)	(clk << ((n) * 2))
 #define DIDSR_PDCS_MASK(n)	(3 << ((n) * 2))