From patchwork Mon Sep 6 18:27:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 12477199 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97DBEC433FE for ; Mon, 6 Sep 2021 18:27:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D5286103B for ; Mon, 6 Sep 2021 18:27:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5D5286103B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DF5D389C03; Mon, 6 Sep 2021 18:27:27 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id E6ECC89BFF; Mon, 6 Sep 2021 18:27:26 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10099"; a="219713107" X-IronPort-AV: E=Sophos;i="5.85,273,1624345200"; d="scan'208";a="219713107" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2021 11:27:26 -0700 X-IronPort-AV: E=Sophos;i="5.85,273,1624345200"; d="scan'208";a="464124876" Received: from ideak-desk.fi.intel.com ([10.237.68.141]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2021 11:27:25 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Nanley G Chery , Juha-Pekka Heikkila , dri-devel@lists.freedesktop.org Subject: [PATCH v2 6/6] drm/fourcc: Add the ADL-P specific pitch requirements of CCS modifiers Date: Mon, 6 Sep 2021 21:27:15 +0300 Message-Id: <20210906182715.3915100-7-imre.deak@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210906182715.3915100-1-imre.deak@intel.com> References: <20210906182715.3915100-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Alderlake-P for all CCS modifiers the main surface pitch must be either 8 Y-tile width or the multiple of 16 Y-tile widths. The CCS surface pitch must be rounded up to power-of-two. Adjust the modifier descriptions accordingly. Cc: Nanley G Chery Cc: Juha-Pekka Heikkila Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak --- include/uapi/drm/drm_fourcc.h | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 45a914850be0d..b63b7fa8bbac6 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -522,8 +522,16 @@ extern "C" { * The main surface is Y-tiled and at plane index 0, the CCS is linear and * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in * main surface. In other words, 4 bits in CCS map to a main surface cache - * line pair. The main surface pitch is required to be a multiple of four - * Y-tile widths. + * line pair. + * + * The pitch of the main surface is required to be either 8 or a multiple of + * 16 Y-tile widths on Alderlake-P and a multiple of 4 Y-tile widths on other + * platforms. + * + * The pitch of the CCS surface must be calculated using the + * ccs_surface_pitch=main_surface_pitch_in_bytes / 512 * 64. + * formula. On Alderlake-P this pitch must be rounded up to be power-of-two + * sized. */ #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) @@ -533,10 +541,12 @@ extern "C" { * The main surface is Y-tiled and at plane index 0, the CCS is linear and * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in * main surface. In other words, 4 bits in CCS map to a main surface cache - * line pair. The main surface pitch is required to be a multiple of four - * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the + * line pair. For semi-planar formats like NV12, CCS planes follow the * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, * planes 2 and 3 for the respective CCS. + * + * About the requirement on the main and CCS surface pitches see the + * description for I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS. */ #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) @@ -554,8 +564,10 @@ extern "C" { * Clear Color value when applicable. The Converted Clear Color values are * consumed by the DE. The last 64 bits are used to store Color Discard Enable * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line - * corresponds to an area of 4x1 tiles in the main surface. The main surface - * pitch is required to be a multiple of 4 tile widths. + * corresponds to an area of 4x1 tiles in the main surface. + * + * About the requirement on the main and CCS surface pitches see the + * description for I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS. */ #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)