From patchwork Thu Sep 30 13:18:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 12528293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C80DDC433EF for ; Thu, 30 Sep 2021 13:19:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9C2136187A for ; Thu, 30 Sep 2021 13:19:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9C2136187A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9F7476EB8B; Thu, 30 Sep 2021 13:19:01 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTPS id F17116EB8B for ; Thu, 30 Sep 2021 13:18:57 +0000 (UTC) X-UUID: 973fccaee5584a37a98ec9f5f8e239f5-20210930 X-UUID: 973fccaee5584a37a98ec9f5f8e239f5-20210930 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2121530296; Thu, 30 Sep 2021 21:18:53 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Sep 2021 21:18:51 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkcas07.mediatek.inc (172.21.101.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Sep 2021 21:18:51 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Sep 2021 21:18:50 +0800 From: Yongqiang Niu To: Chun-Kuang Hu CC: Rob Herring , Matthias Brugger , Philipp Zabel , "David Airlie" , Daniel Vetter , Jassi Brar , Yongqiang Niu , Fabien Parent , Dennis YC Hsieh , , , , , , , Hsin-Yi Wang Subject: [PATCH v2, 1/1] mailbox: cmdq: add instruction time-out interrupt support Date: Thu, 30 Sep 2021 21:18:50 +0800 Message-ID: <20210930131850.21202-2-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930131850.21202-1-yongqiang.niu@mediatek.com> References: <20210930131850.21202-1-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" add time-out cycle setting to make sure time-out interrupt irq will happened when instruction time-out for wait and poll Signed-off-by: Yongqiang Niu --- drivers/mailbox/mtk-cmdq-mailbox.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 64175a893312..197b03222f94 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -36,6 +36,7 @@ #define CMDQ_THR_END_ADDR 0x24 #define CMDQ_THR_WAIT_TOKEN 0x30 #define CMDQ_THR_PRIORITY 0x40 +#define CMDQ_THR_INSTN_TIMEOUT_CYCLES 0x50 #define GCE_GCTL_VALUE 0x48 @@ -54,6 +55,15 @@ #define CMDQ_JUMP_BY_OFFSET 0x10000000 #define CMDQ_JUMP_BY_PA 0x10000001 +/* + * instruction time-out + * cycles to issue instruction time-out interrupt for wait and poll instructions + * GCE axi_clock 156MHz + * 1 cycle = 6.41ns + * instruction time out 2^22*2*6.41ns = 53ms + */ +#define CMDQ_INSTN_TIMEOUT_CYCLES 22 + struct cmdq_thread { struct mbox_chan *chan; void __iomem *base; @@ -376,6 +386,7 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data) writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa, thread->base + CMDQ_THR_END_ADDR); + writel(CMDQ_INSTN_TIMEOUT_CYCLES, thread->base + CMDQ_THR_INSTN_TIMEOUT_CYCLES); writel(thread->priority, thread->base + CMDQ_THR_PRIORITY); writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE); writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);