From patchwork Fri Oct 1 14:34:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris Brezillon X-Patchwork-Id: 12530745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7534EC433F5 for ; Fri, 1 Oct 2021 14:34:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 440E261A50 for ; Fri, 1 Oct 2021 14:34:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 440E261A50 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=collabora.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B9D1F6ED09; Fri, 1 Oct 2021 14:34:37 +0000 (UTC) Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by gabe.freedesktop.org (Postfix) with ESMTPS id 700606ECFF for ; Fri, 1 Oct 2021 14:34:36 +0000 (UTC) Received: from localhost.localdomain (unknown [IPv6:2a01:e0a:2c:6930:5cf4:84a1:2763:fe0d]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: bbrezillon) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id CD7811F457AB; Fri, 1 Oct 2021 15:34:34 +0100 (BST) From: Boris Brezillon To: Joerg Roedel , iommu@lists.linux-foundation.org, Rob Herring , Tomeu Vizoso , Alyssa Rosenzweig , Steven Price , Robin Murphy , Will Deacon , linux-arm-kernel@lists.infradead.org Cc: dri-devel@lists.freedesktop.org, Boris Brezillon Subject: [PATCH v2 2/5] [RFC]iommu/io-pgtable-arm: Take the DEVONLY flag into account on ARM_MALI_LPAE Date: Fri, 1 Oct 2021 16:34:24 +0200 Message-Id: <20211001143427.1564786-3-boris.brezillon@collabora.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211001143427.1564786-1-boris.brezillon@collabora.com> References: <20211001143427.1564786-1-boris.brezillon@collabora.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Restrict the shareability domain when mapping buffers that are GPU-visible only. Signed-off-by: Boris Brezillon --- Flagged RFC because I'm not sure adding a new flag is the right way to convey the 'dev-private buffer' information. --- drivers/iommu/io-pgtable-arm.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index dd9e47189d0d..6ac3defb9ae1 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -450,16 +450,25 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data, << ARM_LPAE_PTE_ATTRINDX_SHIFT); } - /* - * Also Mali has its own notions of shareability wherein its Inner - * domain covers the cores within the GPU, and its Outer domain is - * "outside the GPU" (i.e. either the Inner or System domain in CPU - * terms, depending on coherency). - */ - if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE) + if (data->iop.fmt == ARM_MALI_LPAE) { + /* + * Mali has its own notions of shareability wherein its Inner + * domain covers the cores within the GPU, and its Outer domain + * is "outside the GPU" (i.e. either the Inner or System domain + * in CPU terms, depending on coherency). + * If the mapping is only device-visible, we can use the Inner + * domain, otherwise we need to stick to Outer domain + * shareability. + */ + if (prot & IOMMU_DEVONLY) + pte |= ARM_LPAE_PTE_SH_IS; + else + pte |= ARM_LPAE_PTE_SH_OS; + } else if (prot & IOMMU_CACHE) { pte |= ARM_LPAE_PTE_SH_IS; - else + } else { pte |= ARM_LPAE_PTE_SH_OS; + } if (prot & IOMMU_NOEXEC) pte |= ARM_LPAE_PTE_XN;