From patchwork Mon Oct 11 16:11:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 12550499 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A77DC433EF for ; Mon, 11 Oct 2021 16:10:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E4A8560EB6 for ; Mon, 11 Oct 2021 16:10:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org E4A8560EB6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0A58A6E8F0; Mon, 11 Oct 2021 16:10:20 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id A13A46E8F0; Mon, 11 Oct 2021 16:10:18 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10134"; a="214056829" X-IronPort-AV: E=Sophos;i="5.85,364,1624345200"; d="scan'208";a="214056829" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2021 09:09:55 -0700 X-IronPort-AV: E=Sophos;i="5.85,364,1624345200"; d="scan'208";a="441478029" Received: from ramaling-i9x.iind.intel.com ([10.99.66.205]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2021 09:09:52 -0700 From: Ramalingam C To: dri-devel , intel-gfx Cc: Daniel Vetter , Matthew Auld , CQ Tang , Hellstrom Thomas , Ramalingam C , Daniel Vetter Subject: [PATCH 14/14] Doc/gpu/rfc/i915: i915 DG2 uAPI Date: Mon, 11 Oct 2021 21:41:55 +0530 Message-Id: <20211011161155.6397-15-ramalingam.c@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211011161155.6397-1-ramalingam.c@intel.com> References: <20211011161155.6397-1-ramalingam.c@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Details of the new features getting added as part of DG2 enabling and their implicit impact on the uAPI. Signed-off-by: Ramalingam C cc: Daniel Vetter cc: Matthew Auld --- Documentation/gpu/rfc/i915_dg2.rst | 47 ++++++++++++++++++++++++++++++ Documentation/gpu/rfc/index.rst | 3 ++ 2 files changed, 50 insertions(+) create mode 100644 Documentation/gpu/rfc/i915_dg2.rst diff --git a/Documentation/gpu/rfc/i915_dg2.rst b/Documentation/gpu/rfc/i915_dg2.rst new file mode 100644 index 000000000000..a83ca26cd758 --- /dev/null +++ b/Documentation/gpu/rfc/i915_dg2.rst @@ -0,0 +1,47 @@ +==================== +I915 DG2 RFC Section +==================== + +Upstream plan +============= +Plan to upstream the DG2 enabling is: + +* Merge basic HW enabling for DG2(Still without pciid) +* Merge the 64k support for lmem +* Merge the flat CCS enabling patches +* Add the pciid for DG2 and enable the DG2 in CI + + +64K page support for lmem +========================= +On DG2 hw, local-memory supports minimum GTT page size of 64k only. 4k is not supported anymore. + +DG2 hw dont support the 64k(lmem) and 4k(smem) pages in the same ppgtt Page table. Refer the +struct drm_i915_gem_create_ext for the implication of handling the 64k page size. + +.. kernel-doc:: include/uapi/drm/i915_drm.h + :functions: drm_i915_gem_create_ext + + +flat CCS support for lmem +========================= +Gen 12+ devices support 3D surfaces compression and compression formats. This is +accomplished by an additional compression control state (CCS) stored for each surface. + +Gen 12 devices(TGL and DG1) stores compression state in a separate region of memory. +It is managed by userspace and has an associated set of userspace managed page tables +used by hardware for address translation. + +In Gen 12.5 devices(XEXPSDV and DG2) Flat CCS is introduced to replace the userspace +managed AUX pagetable with the flat indexed region of device memory for storing the +compression state + +GOP Driver steals a chunk of memory for the CCS surface corresponding to the entire +range of local memory. The memory required for the CCS of the entire local memory is +1/256 of the main local memory. The Gop driver will also program a secure register +(XEHPSDV_FLAT_CCS_BASE_ADDR 0x4910) with this address value. + +So the Total local memory available for driver allocation is Total lmem size - CCS data size + +Flat CCS data needs to be cleared when a lmem object is allocated. And CCS data can +be copied in and out of CCS region through XY_CTRL_SURF_COPY_BLT. diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst index 91e93a705230..afb320ed4028 100644 --- a/Documentation/gpu/rfc/index.rst +++ b/Documentation/gpu/rfc/index.rst @@ -20,6 +20,9 @@ host such documentation: i915_gem_lmem.rst +.. toctree:: + i915_dg2.rst + .. toctree:: i915_scheduler.rst