| Message ID | 20211013233632.471892-3-anitha.chrisanthus@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3,1/7] drm/kmb: Work around for higher system clock | expand |
On Wed, Oct 13, 2021 at 04:36:28PM -0700, Anitha Chrisanthus wrote: > From: Edmund Dea <edmund.j.dea@intel.com> > > Don't clear the shared DPHY registers common to MIPI Rx and MIPI Tx during > DSI initialization since this was causing MIPI Rx reset. Rest of the > writes are bitwise, so will not affect Mipi Rx side. > > Fixes: 98521f4d4b4c ("drm/kmb: Mipi DSI part of the display driver") > Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com> > Signed-off-by: Edmund Dea <edmund.j.dea@intel.com> As Edmund is author, he should be listed first. The s-o-b lines expressed the order. With this fixed. Acked-by: Sam Ravnborg <sam@ravnborg.org> > --- > drivers/gpu/drm/kmb/kmb_dsi.c | 5 ----- > 1 file changed, 5 deletions(-) > > diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c > index 86e8e7943e89..a0669b842ff5 100644 > --- a/drivers/gpu/drm/kmb/kmb_dsi.c > +++ b/drivers/gpu/drm/kmb/kmb_dsi.c > @@ -1393,11 +1393,6 @@ int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode, > mipi_tx_init_cfg.lane_rate_mbps = data_rate; > } > > - kmb_write_mipi(kmb_dsi, DPHY_ENABLE, 0); > - kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL0, 0); > - kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL1, 0); > - kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL2, 0); > - > /* Initialize mipi controller */ > mipi_tx_init_cntrl(kmb_dsi, &mipi_tx_init_cfg); > > -- > 2.25.1
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 86e8e7943e89..a0669b842ff5 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -1393,11 +1393,6 @@ int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode, mipi_tx_init_cfg.lane_rate_mbps = data_rate; } - kmb_write_mipi(kmb_dsi, DPHY_ENABLE, 0); - kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL0, 0); - kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL1, 0); - kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL2, 0); - /* Initialize mipi controller */ mipi_tx_init_cntrl(kmb_dsi, &mipi_tx_init_cfg);