diff mbox series

[v3,5/7] drm/kmb: Corrected typo in handle_lcd_irq

Message ID 20211013233632.471892-5-anitha.chrisanthus@intel.com (mailing list archive)
State New, archived
Headers show
Series [v3,1/7] drm/kmb: Work around for higher system clock | expand

Commit Message

Chrisanthus, Anitha Oct. 13, 2021, 11:36 p.m. UTC 
Check for Overflow bits for layer3 in the irq handler.

Fixes: 7f7b96a8a0a1 ("drm/kmb: Add support for KeemBay Display")
Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
---
 drivers/gpu/drm/kmb/kmb_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Sam Ravnborg Oct. 14, 2021, 6:40 p.m. UTC | #1 
Hi Anitha,

On Wed, Oct 13, 2021 at 04:36:30PM -0700, Anitha Chrisanthus wrote:
> Check for Overflow bits for layer3 in the irq handler.
> 
> Fixes: 7f7b96a8a0a1 ("drm/kmb: Add support for KeemBay Display")
> Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>

Obvious fix,
Acked-by: Sam Ravnborg <sam@ravnborg.org>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 12ce669650cc..961ac6fb5fcf 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -380,7 +380,7 @@  static irqreturn_t handle_lcd_irq(struct drm_device *dev)
 		if (val & LAYER3_DMA_FIFO_UNDERFLOW)
 			drm_dbg(&kmb->drm,
 				"LAYER3:GL1 DMA UNDERFLOW val = 0x%lx", val);
-		if (val & LAYER3_DMA_FIFO_UNDERFLOW)
+		if (val & LAYER3_DMA_FIFO_OVERFLOW)
 			drm_dbg(&kmb->drm,
 				"LAYER3:GL1 DMA OVERFLOW val = 0x%lx", val);
 	}