| Message ID | 20211026052916.8222-6-jason-jh.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | CMDQ refinement of Mediatek DRM driver | expand |
Hi, Jason: jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年10月26日 週二 下午1:29寫道： > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > In cmdq mode, packet may be flushed before it is executed, so > the pending flag should be cleared after cmdq packet is done. Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 51 ++++++++++++++++++++++--- > 1 file changed, 46 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index 31f05efc1bc0..ea285795776f 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -275,8 +275,42 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, > #if IS_REACHABLE(CONFIG_MTK_CMDQ) > static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg) > { > + struct cmdq_cb_data *data = mssg; > struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client); > struct mtk_drm_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_drm_crtc, cmdq_client); > + struct mtk_crtc_state *state; > + unsigned int i; > + > + if (data->sta < 0) > + return; > + > + state = to_mtk_crtc_state(mtk_crtc->base.state); > + > + state->pending_config = false; > + > + if (mtk_crtc->pending_planes) { > + for (i = 0; i < mtk_crtc->layer_nr; i++) { > + struct drm_plane *plane = &mtk_crtc->planes[i]; > + struct mtk_plane_state *plane_state; > + > + plane_state = to_mtk_plane_state(plane->state); > + > + plane_state->pending.config = false; > + } > + mtk_crtc->pending_planes = false; > + } > + > + if (mtk_crtc->pending_async_planes) { > + for (i = 0; i < mtk_crtc->layer_nr; i++) { > + struct drm_plane *plane = &mtk_crtc->planes[i]; > + struct mtk_plane_state *plane_state; > + > + plane_state = to_mtk_plane_state(plane->state); > + > + plane_state->pending.async_config = false; > + } > + mtk_crtc->pending_async_planes = false; > + } > > mtk_crtc->cmdq_vblank_cnt = 0; > } > @@ -432,7 +466,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, > state->pending_vrefresh, 0, > cmdq_handle); > > - state->pending_config = false; > + if (!cmdq_handle) > + state->pending_config = false; > } > > if (mtk_crtc->pending_planes) { > @@ -452,9 +487,12 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, > mtk_ddp_comp_layer_config(comp, local_layer, > plane_state, > cmdq_handle); > - plane_state->pending.config = false; > + if (!cmdq_handle) > + plane_state->pending.config = false; > } > - mtk_crtc->pending_planes = false; > + > + if (!cmdq_handle) > + mtk_crtc->pending_planes = false; > } > > if (mtk_crtc->pending_async_planes) { > @@ -474,9 +512,12 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, > mtk_ddp_comp_layer_config(comp, local_layer, > plane_state, > cmdq_handle); > - plane_state->pending.async_config = false; > + if (!cmdq_handle) > + plane_state->pending.async_config = false; > } > - mtk_crtc->pending_async_planes = false; > + > + if (!cmdq_handle) > + mtk_crtc->pending_async_planes = false; > } > } > > -- > 2.18.0 >
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 31f05efc1bc0..ea285795776f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -275,8 +275,42 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, #if IS_REACHABLE(CONFIG_MTK_CMDQ) static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg) { + struct cmdq_cb_data *data = mssg; struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client); struct mtk_drm_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_drm_crtc, cmdq_client); + struct mtk_crtc_state *state; + unsigned int i; + + if (data->sta < 0) + return; + + state = to_mtk_crtc_state(mtk_crtc->base.state); + + state->pending_config = false; + + if (mtk_crtc->pending_planes) { + for (i = 0; i < mtk_crtc->layer_nr; i++) { + struct drm_plane *plane = &mtk_crtc->planes[i]; + struct mtk_plane_state *plane_state; + + plane_state = to_mtk_plane_state(plane->state); + + plane_state->pending.config = false; + } + mtk_crtc->pending_planes = false; + } + + if (mtk_crtc->pending_async_planes) { + for (i = 0; i < mtk_crtc->layer_nr; i++) { + struct drm_plane *plane = &mtk_crtc->planes[i]; + struct mtk_plane_state *plane_state; + + plane_state = to_mtk_plane_state(plane->state); + + plane_state->pending.async_config = false; + } + mtk_crtc->pending_async_planes = false; + } mtk_crtc->cmdq_vblank_cnt = 0; } @@ -432,7 +466,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, state->pending_vrefresh, 0, cmdq_handle); - state->pending_config = false; + if (!cmdq_handle) + state->pending_config = false; } if (mtk_crtc->pending_planes) { @@ -452,9 +487,12 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, mtk_ddp_comp_layer_config(comp, local_layer, plane_state, cmdq_handle); - plane_state->pending.config = false; + if (!cmdq_handle) + plane_state->pending.config = false; } - mtk_crtc->pending_planes = false; + + if (!cmdq_handle) + mtk_crtc->pending_planes = false; } if (mtk_crtc->pending_async_planes) { @@ -474,9 +512,12 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, mtk_ddp_comp_layer_config(comp, local_layer, plane_state, cmdq_handle); - plane_state->pending.async_config = false; + if (!cmdq_handle) + plane_state->pending.async_config = false; } - mtk_crtc->pending_async_planes = false; + + if (!cmdq_handle) + mtk_crtc->pending_async_planes = false; } }