From patchwork Wed Nov 17 14:33:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 12626135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD985C433F5 for ; Thu, 18 Nov 2021 07:29:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AC89D610C8 for ; Thu, 18 Nov 2021 07:29:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org AC89D610C8 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EAB426EAAB; Thu, 18 Nov 2021 07:28:38 +0000 (UTC) Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by gabe.freedesktop.org (Postfix) with ESMTPS id A5BCD6E334 for ; Wed, 17 Nov 2021 14:34:18 +0000 (UTC) Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mnM0e-0005td-FR; Wed, 17 Nov 2021 15:34:00 +0100 Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1mnM0b-001P6H-2C; Wed, 17 Nov 2021 15:33:57 +0100 From: Sascha Hauer To: dri-devel@lists.freedesktop.org Subject: [PATCH 04/12] drm/rockchip: dw_hdmi: add regulator support Date: Wed, 17 Nov 2021 15:33:39 +0100 Message-Id: <20211117143347.314294-5-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211117143347.314294-1-s.hauer@pengutronix.de> References: <20211117143347.314294-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: dri-devel@lists.freedesktop.org X-Mailman-Approved-At: Thu, 18 Nov 2021 07:28:27 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Benjamin Gaignard , Sascha Hauer , Sandy Huang , linux-rockchip@lists.infradead.org, Michael Riesch , kernel@pengutronix.de, Peter Geis , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The RK3568 has HDMI_TX_AVDD0V9 and HDMI_TX_AVDD_1V8 supply inputs needed for the HDMI port. add support for these to the driver for boards which have them supplied by switchable regulators. Signed-off-by: Sascha Hauer --- .../display/rockchip/rockchip,dw-hdmi.yaml | 6 ++ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 58 ++++++++++++++++++- 2 files changed, 61 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml index 53fa42479d5b7..293b2cfbf739f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml @@ -28,6 +28,12 @@ properties: reg-io-width: const: 4 + avdd-0v9-supply: + description: A 0.9V supply that powers up the SoC internal circuitry. + + avdd-1v8-supply: + description: A 0.9V supply that powers up the SoC internal circuitry. + clocks: minItems: 2 items: diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 29608c25e2d0e..b8fe56c89cdc9 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -83,6 +84,8 @@ struct rockchip_hdmi { struct clk *vpll_clk; struct clk *grf_clk; struct dw_hdmi *hdmi; + struct regulator *avdd_0v9; + struct regulator *avdd_1v8; struct phy *phy; }; @@ -222,6 +225,22 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) hdmi->vpll_clk = hdmi->clks[RK_HDMI_CLK_VPLL].clk; hdmi->grf_clk = hdmi->clks[RK_HDMI_CLK_GRF].clk; + hdmi->avdd_0v9 = devm_regulator_get_optional(hdmi->dev, "avdd-0v9"); + if (IS_ERR(hdmi->avdd_0v9)) { + if (PTR_ERR(hdmi->avdd_0v9) != -ENODEV) + return PTR_ERR(hdmi->avdd_0v9); + + hdmi->avdd_0v9 = NULL; + } + + hdmi->avdd_1v8 = devm_regulator_get_optional(hdmi->dev, "avdd-1v8"); + if (IS_ERR(hdmi->avdd_1v8)) { + if (PTR_ERR(hdmi->avdd_1v8) != -ENODEV) + return PTR_ERR(hdmi->avdd_1v8); + + hdmi->avdd_1v8 = NULL; + } + return 0; } @@ -559,11 +578,27 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, return ret; } + if (hdmi->avdd_0v9) { + ret = regulator_enable(hdmi->avdd_0v9); + if (ret) { + DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret); + goto err_avdd_0v9; + } + } + + if (hdmi->avdd_1v8) { + ret = regulator_enable(hdmi->avdd_1v8); + if (ret) { + DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret); + goto err_avdd_1v8; + } + } + ret = clk_bulk_prepare_enable(RK_HDMI_NCLOCKS_HDMI, hdmi->clks); if (ret) { DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret); - return ret; + goto err_clk; } if (hdmi->chip_data == &rk3568_chip_data) { @@ -587,10 +622,21 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, */ if (IS_ERR(hdmi->hdmi)) { ret = PTR_ERR(hdmi->hdmi); - drm_encoder_cleanup(encoder); - clk_bulk_disable_unprepare(RK_HDMI_NCLOCKS_HDMI, hdmi->clks); + goto err_bind; } + return 0; + +err_bind: + clk_bulk_disable_unprepare(RK_HDMI_NCLOCKS_HDMI, hdmi->clks); + drm_encoder_cleanup(encoder); +err_clk: + if (hdmi->avdd_1v8) + regulator_disable(hdmi->avdd_1v8); +err_avdd_1v8: + if (hdmi->avdd_0v9) + regulator_disable(hdmi->avdd_0v9); +err_avdd_0v9: return ret; } @@ -601,6 +647,12 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, dw_hdmi_unbind(hdmi->hdmi); clk_bulk_disable_unprepare(RK_HDMI_NCLOCKS_HDMI, hdmi->clks); + + if (hdmi->avdd_1v8) + regulator_disable(hdmi->avdd_1v8); + + if (hdmi->avdd_0v9) + regulator_disable(hdmi->avdd_0v9); } static const struct component_ops dw_hdmi_rockchip_ops = {