| Message ID | 20211126093514.927340-1-kieran.bingham+renesas@ideasonboard.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm: rcar-du: crtc: Support external DSI dot clock | expand |
Hi Kieran, Thank you for the patch. On Fri, Nov 26, 2021 at 09:35:14AM +0000, Kieran Bingham wrote: > On platforms with an external clock, both the group and crtc must be > handled accordingly to correctly pass through the external clock and > configure the DU to use the external rate. > > The CRTC support was missed while adding the DSI support on the r8a779a0 > which led to the output clocks being incorrectly determined. > > Ensure that when a CRTC is routed through the DSI encoder, the external > clock is used without any further divider being applied. > > Fixes: b291fdcf5114 ("drm: rcar-du: Add r8a779a0 device support") > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c > index 5672830ca184..5236f917cc68 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c > +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c > @@ -261,12 +261,13 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) > rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr); > > escr = ESCR_DCLKSEL_DCLKIN | div; > - } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) { > + } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) || > + rcdu->info->dsi_clk_mask & BIT(rcrtc->index)) { > /* > - * Use the LVDS PLL output as the dot clock when outputting to > - * the LVDS encoder on an SoC that supports this clock routing > - * option. We use the clock directly in that case, without any > - * additional divider. > + * Use the external LVDS or DSI PLL output as the dot clock when > + * outputting to the LVDS or DSI encoder on an SoC that supports > + * this clock routing option. We use the clock directly in that > + * case, without any additional divider. > */ > escr = ESCR_DCLKSEL_DCLKIN; > } else {
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 5672830ca184..5236f917cc68 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -261,12 +261,13 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr); escr = ESCR_DCLKSEL_DCLKIN | div; - } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) { + } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) || + rcdu->info->dsi_clk_mask & BIT(rcrtc->index)) { /* - * Use the LVDS PLL output as the dot clock when outputting to - * the LVDS encoder on an SoC that supports this clock routing - * option. We use the clock directly in that case, without any - * additional divider. + * Use the external LVDS or DSI PLL output as the dot clock when + * outputting to the LVDS or DSI encoder on an SoC that supports + * this clock routing option. We use the clock directly in that + * case, without any additional divider. */ escr = ESCR_DCLKSEL_DCLKIN; } else {
On platforms with an external clock, both the group and crtc must be handled accordingly to correctly pass through the external clock and configure the DU to use the external rate. The CRTC support was missed while adding the DSI support on the r8a779a0 which led to the output clocks being incorrectly determined. Ensure that when a CRTC is routed through the DSI encoder, the external clock is used without any further divider being applied. Fixes: b291fdcf5114 ("drm: rcar-du: Add r8a779a0 device support") Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)