diff mbox series

[1/4] drm/i915: Add has_64k_pages flag

Message ID 20211207165156.31244-2-ramalingam.c@intel.com (mailing list archive)
State New, archived
Headers show
Series Basic enabling of 64k page support | expand

Commit Message

Ramalingam C Dec. 7, 2021, 4:51 p.m. UTC 
From: Stuart Summers <stuart.summers@intel.com>

Add a new platform flag, has_64k_pages, for platforms supporting
base page sizes of 64k.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 2 ++
 drivers/gpu/drm/i915/i915_pci.c          | 2 ++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 5 insertions(+)

Comments

Thomas Hellström (Intel) Dec. 8, 2021, 12:43 p.m. UTC | #1 
Hi,

On 12/7/21 17:51, Ramalingam C wrote:
> From: Stuart Summers <stuart.summers@intel.com>
>
> Add a new platform flag, has_64k_pages, for platforms supporting
> base page sizes of 64k.
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h          | 2 ++
>   drivers/gpu/drm/i915/i915_pci.c          | 2 ++
>   drivers/gpu/drm/i915/intel_device_info.h | 1 +
>   3 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 85bb8d3107f0..6132163e1cb3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1528,6 +1528,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   #define HAS_MSLICES(dev_priv) \
>   	(INTEL_INFO(dev_priv)->has_mslices)
>   
> +#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
> +

Could we please have some documentation of the exact meaning of this flag.
Like, smallest page size of LMEM is 64K. Hardware supports 64k pages etc?

for future reference.

/Thomas





>   #define HAS_IPC(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ipc)
>   
>   #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 6aaa7c644c9b..634282edadb7 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1029,6 +1029,7 @@ static const struct intel_device_info xehpsdv_info = {
>   	DGFX_FEATURES,
>   	PLATFORM(INTEL_XEHPSDV),
>   	.display = { },
> +	.has_64k_pages = 1,
>   	.pipe_mask = 0,
>   	.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) |
> @@ -1047,6 +1048,7 @@ static const struct intel_device_info dg2_info = {
>   	.graphics.rel = 55,
>   	.media.rel = 55,
>   	PLATFORM(INTEL_DG2),
> +	.has_64k_pages = 1,
>   	.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) |
>   		BIT(VECS0) | BIT(VECS1) |
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 669f0d26c3c3..f38ac5bd837b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -123,6 +123,7 @@ enum intel_ppgtt_type {
>   	func(is_dgfx); \
>   	/* Keep has_* in alphabetical order */ \
>   	func(has_64bit_reloc); \
> +	func(has_64k_pages); \
>   	func(gpu_reset_clobbers_display); \
>   	func(has_reset_engine); \
>   	func(has_global_mocs); \
Matthew Auld Dec. 8, 2021, 12:59 p.m. UTC | #2 
On Wed, 8 Dec 2021 at 12:43, Thomas Hellström (Intel)
<thomas_os@shipmail.org> wrote:
>
> Hi,
>
> On 12/7/21 17:51, Ramalingam C wrote:
> > From: Stuart Summers <stuart.summers@intel.com>
> >
> > Add a new platform flag, has_64k_pages, for platforms supporting
> > base page sizes of 64k.
> >
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_drv.h          | 2 ++
> >   drivers/gpu/drm/i915/i915_pci.c          | 2 ++
> >   drivers/gpu/drm/i915/intel_device_info.h | 1 +
> >   3 files changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 85bb8d3107f0..6132163e1cb3 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1528,6 +1528,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >   #define HAS_MSLICES(dev_priv) \
> >       (INTEL_INFO(dev_priv)->has_mslices)
> >
> > +#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
> > +
>
> Could we please have some documentation of the exact meaning of this flag.
> Like, smallest page size of LMEM is 64K. Hardware supports 64k pages etc?

Something like: "Set if the device requires 64K GTT page sizes or
larger for device local memory access. Also implies that we require or
at least support the compact PT layout for the ppGTT when using 64K
GTT pages."

>
> for future reference.
>
> /Thomas
>
>
>
>
>
> >   #define HAS_IPC(dev_priv)            (INTEL_INFO(dev_priv)->display.has_ipc)
> >
> >   #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index 6aaa7c644c9b..634282edadb7 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -1029,6 +1029,7 @@ static const struct intel_device_info xehpsdv_info = {
> >       DGFX_FEATURES,
> >       PLATFORM(INTEL_XEHPSDV),
> >       .display = { },
> > +     .has_64k_pages = 1,
> >       .pipe_mask = 0,
> >       .platform_engine_mask =
> >               BIT(RCS0) | BIT(BCS0) |
> > @@ -1047,6 +1048,7 @@ static const struct intel_device_info dg2_info = {
> >       .graphics.rel = 55,
> >       .media.rel = 55,
> >       PLATFORM(INTEL_DG2),
> > +     .has_64k_pages = 1,
> >       .platform_engine_mask =
> >               BIT(RCS0) | BIT(BCS0) |
> >               BIT(VECS0) | BIT(VECS1) |
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 669f0d26c3c3..f38ac5bd837b 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -123,6 +123,7 @@ enum intel_ppgtt_type {
> >       func(is_dgfx); \
> >       /* Keep has_* in alphabetical order */ \
> >       func(has_64bit_reloc); \
> > +     func(has_64k_pages); \
> >       func(gpu_reset_clobbers_display); \
> >       func(has_reset_engine); \
> >       func(has_global_mocs); \
Thomas Hellström (Intel) Dec. 8, 2021, 1:22 p.m. UTC | #3 
On 12/8/21 13:59, Matthew Auld wrote:
> On Wed, 8 Dec 2021 at 12:43, Thomas Hellström (Intel)
> <thomas_os@shipmail.org> wrote:
>> Hi,
>>
>> On 12/7/21 17:51, Ramalingam C wrote:
>>> From: Stuart Summers <stuart.summers@intel.com>
>>>
>>> Add a new platform flag, has_64k_pages, for platforms supporting
>>> base page sizes of 64k.
>>>
>>> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
>>> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>>> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/i915_drv.h          | 2 ++
>>>    drivers/gpu/drm/i915/i915_pci.c          | 2 ++
>>>    drivers/gpu/drm/i915/intel_device_info.h | 1 +
>>>    3 files changed, 5 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index 85bb8d3107f0..6132163e1cb3 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -1528,6 +1528,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>>    #define HAS_MSLICES(dev_priv) \
>>>        (INTEL_INFO(dev_priv)->has_mslices)
>>>
>>> +#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
>>> +
>> Could we please have some documentation of the exact meaning of this flag.
>> Like, smallest page size of LMEM is 64K. Hardware supports 64k pages etc?
> Something like: "Set if the device requires 64K GTT page sizes or
> larger for device local memory access. Also implies that we require or
> at least support the compact PT layout for the ppGTT when using 64K
> GTT pages."

Sounds great.

Thanks,

Thomas
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 85bb8d3107f0..6132163e1cb3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1528,6 +1528,8 @@  IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_MSLICES(dev_priv) \
 	(INTEL_INFO(dev_priv)->has_mslices)
 
+#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
+
 #define HAS_IPC(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ipc)
 
 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 6aaa7c644c9b..634282edadb7 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1029,6 +1029,7 @@  static const struct intel_device_info xehpsdv_info = {
 	DGFX_FEATURES,
 	PLATFORM(INTEL_XEHPSDV),
 	.display = { },
+	.has_64k_pages = 1,
 	.pipe_mask = 0,
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) |
@@ -1047,6 +1048,7 @@  static const struct intel_device_info dg2_info = {
 	.graphics.rel = 55,
 	.media.rel = 55,
 	PLATFORM(INTEL_DG2),
+	.has_64k_pages = 1,
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) |
 		BIT(VECS0) | BIT(VECS1) |
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 669f0d26c3c3..f38ac5bd837b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -123,6 +123,7 @@  enum intel_ppgtt_type {
 	func(is_dgfx); \
 	/* Keep has_* in alphabetical order */ \
 	func(has_64bit_reloc); \
+	func(has_64k_pages); \
 	func(gpu_reset_clobbers_display); \
 	func(has_reset_engine); \
 	func(has_global_mocs); \