diff mbox series

[4/4] drm/i915: enforce min page size for scratch

Message ID 20211207165156.31244-5-ramalingam.c@intel.com (mailing list archive)
State New, archived
Headers show
Series Basic enabling of 64k page support | expand

Commit Message

Ramalingam C Dec. 7, 2021, 4:51 p.m. UTC 
From: Matthew Auld <matthew.auld@intel.com>

If the device needs 64K minimum GTT pages for device local-memory,
like on XEHPSDV, then we need to fail the allocation if we can't
meet it, instead of falling back to 4K pages, otherwise we can't
safely support the insertion of device local-memory pages for
this vm, since the HW expects the correct physical alignment and
size for every PTE, if we mark the page-table as 64K GTT mode.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gtt.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Thomas Hellstrom Dec. 8, 2021, 1:32 p.m. UTC | #1 
On 12/7/21 17:51, Ramalingam C wrote:
> From: Matthew Auld <matthew.auld@intel.com>
>
> If the device needs 64K minimum GTT pages for device local-memory,
> like on XEHPSDV, then we need to fail the allocation if we can't
> meet it, instead of falling back to 4K pages, otherwise we can't
> safely support the insertion of device local-memory pages for
> this vm, since the HW expects the correct physical alignment and
> size for every PTE, if we mark the page-table as 64K GTT mode.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_gtt.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 1428e2b9075a..869b771a5fdc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -337,6 +337,18 @@ int setup_scratch_page(struct i915_address_space *vm)
>   		if (size == I915_GTT_PAGE_SIZE_4K)
>   			return -ENOMEM;
>   
> +		/*
> +		 * If we need 64K minimum GTT pages for device local-memory,
> +		 * like on XEHPSDV, then we need to fail the allocation here,
> +		 * otherwise we can't safely support the insertion of
> +		 * local-memory pages for this vm, since the HW expects the
> +		 * correct physical alignment and size when the page-table is
> +		 * operating in 64K GTT mode, which includes any scratch PTEs,
> +		 * since userpsace can still touch them.

s/userpsace/userspace/

LGTM.

Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

> +		 */
> +		if (HAS_64K_PAGES(vm->i915))
> +			return -ENOMEM;
> +
>   		size = I915_GTT_PAGE_SIZE_4K;
>   	} while (1);
>   }
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 1428e2b9075a..869b771a5fdc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -337,6 +337,18 @@  int setup_scratch_page(struct i915_address_space *vm)
 		if (size == I915_GTT_PAGE_SIZE_4K)
 			return -ENOMEM;
 
+		/*
+		 * If we need 64K minimum GTT pages for device local-memory,
+		 * like on XEHPSDV, then we need to fail the allocation here,
+		 * otherwise we can't safely support the insertion of
+		 * local-memory pages for this vm, since the HW expects the
+		 * correct physical alignment and size when the page-table is
+		 * operating in 64K GTT mode, which includes any scratch PTEs,
+		 * since userpsace can still touch them.
+		 */
+		if (HAS_64K_PAGES(vm->i915))
+			return -ENOMEM;
+
 		size = I915_GTT_PAGE_SIZE_4K;
 	} while (1);
 }