| Message ID | 20211208141613.7251-2-ramalingam.c@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Basic enabling of 64k page support | expand |
Hi Ram, Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> but just two notes on the patchstyle, no need to resend: 1. would be nice to have [PATCH v2...] otherwise it's difficult to see if I'm reading the correct version. (I don't see the difficulty 'git format-patch -v 2...') > Add a new platform flag, has_64k_pages, to mark the requirement of 64K > GTT page sizes or larger for device local memory access. > > Also implies that we require or at least support the compact PT layout > for the ppGTT when using 64K GTT pages. > > v2: More explanation for the flag [Thomas] > > Signed-off-by: Stuart Summers <stuart.summers@intel.com> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> 2. the tag part has a temporal meaning: Stuart has written the patch, Lucas has reviewed it and you are sending it, therefore, the correct order should be: Signed-off-by: Stuart Summers <stuart.summers@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Thanks, Andi
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 85bb8d3107f0..e63c62f69ec5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1528,6 +1528,14 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_MSLICES(dev_priv) \ (INTEL_INFO(dev_priv)->has_mslices) +/* + * Set this flag, when platform requires 64K GTT page sizes or larger for + * device local memory access. Also this flag implies that we require or + * at least support the compact PT layout for the ppGTT when using the 64K + * GTT pages. + */ +#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages) + #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 6aaa7c644c9b..634282edadb7 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1029,6 +1029,7 @@ static const struct intel_device_info xehpsdv_info = { DGFX_FEATURES, PLATFORM(INTEL_XEHPSDV), .display = { }, + .has_64k_pages = 1, .pipe_mask = 0, .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | @@ -1047,6 +1048,7 @@ static const struct intel_device_info dg2_info = { .graphics.rel = 55, .media.rel = 55, PLATFORM(INTEL_DG2), + .has_64k_pages = 1, .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VECS1) | diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 669f0d26c3c3..f38ac5bd837b 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -123,6 +123,7 @@ enum intel_ppgtt_type { func(is_dgfx); \ /* Keep has_* in alphabetical order */ \ func(has_64bit_reloc); \ + func(has_64k_pages); \ func(gpu_reset_clobbers_display); \ func(has_reset_engine); \ func(has_global_mocs); \