| Message ID | 20220120182413.8074-1-matthew.brost@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/guc: Don't check CT descriptor status before CT write / read | expand |
Hi Matthew,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip drm-exynos/exynos-drm-next drm/drm-next tegra-drm/drm/tegra/for-next v5.16 next-20220120]
[cannot apply to airlied/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Matthew-Brost/drm-i915-guc-Don-t-check-CT-descriptor-status-before-CT-write-read/20220121-023033
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-r002-20220117 (https://download.01.org/0day-ci/archive/20220121/202201211022.gq2U1jNs-lkp@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project f7b7138a62648f4019c55e4671682af1f851f295)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/0311a8b0f99c50ab1a666a5cdbe2b1a0a2c3c71d
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Matthew-Brost/drm-i915-guc-Don-t-check-CT-descriptor-status-before-CT-write-read/20220121-023033
git checkout 0311a8b0f99c50ab1a666a5cdbe2b1a0a2c3c71d
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:469:1: warning: unused label 'corrupted' [-Wunused-label]
corrupted:
^~~~~~~~~~
1 warning generated.
vim +/corrupted +469 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 422
1d407096002bec drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2018-03-26 423 /*
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 424 * dw0: CT header (including fence)
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 425 * dw1: HXG header (including action code)
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 426 * dw2+: action data
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 427 */
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 428 header = FIELD_PREP(GUC_CTB_MSG_0_FORMAT, GUC_CTB_FORMAT_HXG) |
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 429 FIELD_PREP(GUC_CTB_MSG_0_NUM_DWORDS, len) |
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 430 FIELD_PREP(GUC_CTB_MSG_0_FENCE, fence);
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 431
1681924d8bdeb2 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 432 type = (flags & INTEL_GUC_CT_SEND_NB) ? GUC_HXG_TYPE_EVENT :
1681924d8bdeb2 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 433 GUC_HXG_TYPE_REQUEST;
1681924d8bdeb2 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 434 hxg = FIELD_PREP(GUC_HXG_MSG_0_TYPE, type) |
1681924d8bdeb2 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 435 FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |
1681924d8bdeb2 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 436 GUC_HXG_EVENT_MSG_0_DATA0, action[0]);
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 437
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 438 CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 439 tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
0a015ff9730c16 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2018-03-26 440
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 441 cmds[tail] = header;
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 442 tail = (tail + 1) % size;
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 443
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 444 cmds[tail] = hxg;
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 445 tail = (tail + 1) % size;
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 446
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 447 for (i = 1; i < len; i++) {
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 448 cmds[tail] = action[i];
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 449 tail = (tail + 1) % size;
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 450 }
4c22abfbcb8456 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2020-01-20 451 GEM_BUG_ON(tail > size);
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 452
d35ca600873eeb drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 453 /*
d35ca600873eeb drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 454 * make sure H2G buffer update and LRC tail update (if this triggering a
d35ca600873eeb drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 455 * submission) are visible before updating the descriptor tail
d35ca600873eeb drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 456 */
6b540bf6f14362 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-10-14 457 intel_guc_write_barrier(ct_to_guc(ct));
d35ca600873eeb drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 458
75452167a2794c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 459 /* update local copies */
75452167a2794c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 460 ctb->tail = tail;
f4eb1f3fe94683 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-21 461 GEM_BUG_ON(atomic_read(&ctb->space) < len + GUC_CTB_HDR_LEN);
f4eb1f3fe94683 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-21 462 atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space);
75452167a2794c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 463
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 464 /* now update descriptor */
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 465 WRITE_ONCE(desc->tail, tail);
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 466
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 467 return 0;
4c22abfbcb8456 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2020-01-20 468
4c22abfbcb8456 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2020-01-20 @469 corrupted:
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 470 CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 471 desc->head, desc->tail, desc->status);
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 472 ctb->broken = true;
4c22abfbcb8456 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2020-01-20 473 return -EPIPE;
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 474 }
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 475
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
Hi Matthew,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next drm/drm-next tegra-drm/drm/tegra/for-next v5.16 next-20220121]
[cannot apply to airlied/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Matthew-Brost/drm-i915-guc-Don-t-check-CT-descriptor-status-before-CT-write-read/20220121-023033
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-defconfig (https://download.01.org/0day-ci/archive/20220121/202201211326.Zspu6s33-lkp@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/0311a8b0f99c50ab1a666a5cdbe2b1a0a2c3c71d
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Matthew-Brost/drm-i915-guc-Don-t-check-CT-descriptor-status-before-CT-write-read/20220121-023033
git checkout 0311a8b0f99c50ab1a666a5cdbe2b1a0a2c3c71d
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c: In function 'ct_write':
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:469:1: error: label 'corrupted' defined but not used [-Werror=unused-label]
469 | corrupted:
| ^~~~~~~~~
cc1: all warnings being treated as errors
vim +/corrupted +469 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 422
1d407096002beca drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2018-03-26 423 /*
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 424 * dw0: CT header (including fence)
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 425 * dw1: HXG header (including action code)
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 426 * dw2+: action data
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 427 */
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 428 header = FIELD_PREP(GUC_CTB_MSG_0_FORMAT, GUC_CTB_FORMAT_HXG) |
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 429 FIELD_PREP(GUC_CTB_MSG_0_NUM_DWORDS, len) |
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 430 FIELD_PREP(GUC_CTB_MSG_0_FENCE, fence);
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 431
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 432 type = (flags & INTEL_GUC_CT_SEND_NB) ? GUC_HXG_TYPE_EVENT :
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 433 GUC_HXG_TYPE_REQUEST;
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 434 hxg = FIELD_PREP(GUC_HXG_MSG_0_TYPE, type) |
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 435 FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 436 GUC_HXG_EVENT_MSG_0_DATA0, action[0]);
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 437
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 438 CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 439 tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
0a015ff9730c169 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2018-03-26 440
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 441 cmds[tail] = header;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 442 tail = (tail + 1) % size;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 443
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 444 cmds[tail] = hxg;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 445 tail = (tail + 1) % size;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 446
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 447 for (i = 1; i < len; i++) {
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 448 cmds[tail] = action[i];
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 449 tail = (tail + 1) % size;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 450 }
4c22abfbcb8456d drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2020-01-20 451 GEM_BUG_ON(tail > size);
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 452
d35ca600873eebc drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 453 /*
d35ca600873eebc drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 454 * make sure H2G buffer update and LRC tail update (if this triggering a
d35ca600873eebc drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 455 * submission) are visible before updating the descriptor tail
d35ca600873eebc drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 456 */
6b540bf6f14362a drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-10-14 457 intel_guc_write_barrier(ct_to_guc(ct));
d35ca600873eebc drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 458
75452167a2794c3 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 459 /* update local copies */
75452167a2794c3 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 460 ctb->tail = tail;
f4eb1f3fe94683c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-21 461 GEM_BUG_ON(atomic_read(&ctb->space) < len + GUC_CTB_HDR_LEN);
f4eb1f3fe94683c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-21 462 atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space);
75452167a2794c3 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 463
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 464 /* now update descriptor */
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 465 WRITE_ONCE(desc->tail, tail);
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 466
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 467 return 0;
4c22abfbcb8456d drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2020-01-20 468
4c22abfbcb8456d drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2020-01-20 @469 corrupted:
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 470 CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 471 desc->head, desc->tail, desc->status);
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 472 ctb->broken = true;
4c22abfbcb8456d drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2020-01-20 473 return -EPIPE;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 474 }
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 475
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
Hi Matthew,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next drm/drm-next tegra-drm/drm/tegra/for-next v5.16 next-20220121]
[cannot apply to airlied/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Matthew-Brost/drm-i915-guc-Don-t-check-CT-descriptor-status-before-CT-write-read/20220121-023033
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a005-20220117 (https://download.01.org/0day-ci/archive/20220121/202201211310.Npkld1YY-lkp@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project f7b7138a62648f4019c55e4671682af1f851f295)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/0311a8b0f99c50ab1a666a5cdbe2b1a0a2c3c71d
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Matthew-Brost/drm-i915-guc-Don-t-check-CT-descriptor-status-before-CT-write-read/20220121-023033
git checkout 0311a8b0f99c50ab1a666a5cdbe2b1a0a2c3c71d
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:469:1: error: unused label 'corrupted' [-Werror,-Wunused-label]
corrupted:
^~~~~~~~~~
1 error generated.
vim +/corrupted +469 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 422
1d407096002beca drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2018-03-26 423 /*
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 424 * dw0: CT header (including fence)
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 425 * dw1: HXG header (including action code)
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 426 * dw2+: action data
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 427 */
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 428 header = FIELD_PREP(GUC_CTB_MSG_0_FORMAT, GUC_CTB_FORMAT_HXG) |
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 429 FIELD_PREP(GUC_CTB_MSG_0_NUM_DWORDS, len) |
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 430 FIELD_PREP(GUC_CTB_MSG_0_FENCE, fence);
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 431
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 432 type = (flags & INTEL_GUC_CT_SEND_NB) ? GUC_HXG_TYPE_EVENT :
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 433 GUC_HXG_TYPE_REQUEST;
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 434 hxg = FIELD_PREP(GUC_HXG_MSG_0_TYPE, type) |
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 435 FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 436 GUC_HXG_EVENT_MSG_0_DATA0, action[0]);
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 437
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 438 CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 439 tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
0a015ff9730c169 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2018-03-26 440
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 441 cmds[tail] = header;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 442 tail = (tail + 1) % size;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 443
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 444 cmds[tail] = hxg;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 445 tail = (tail + 1) % size;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 446
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 447 for (i = 1; i < len; i++) {
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 448 cmds[tail] = action[i];
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 449 tail = (tail + 1) % size;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 450 }
4c22abfbcb8456d drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2020-01-20 451 GEM_BUG_ON(tail > size);
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 452
d35ca600873eebc drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 453 /*
d35ca600873eebc drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 454 * make sure H2G buffer update and LRC tail update (if this triggering a
d35ca600873eebc drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 455 * submission) are visible before updating the descriptor tail
d35ca600873eebc drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 456 */
6b540bf6f14362a drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-10-14 457 intel_guc_write_barrier(ct_to_guc(ct));
d35ca600873eebc drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-06-02 458
75452167a2794c3 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 459 /* update local copies */
75452167a2794c3 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 460 ctb->tail = tail;
f4eb1f3fe94683c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-21 461 GEM_BUG_ON(atomic_read(&ctb->space) < len + GUC_CTB_HDR_LEN);
f4eb1f3fe94683c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-21 462 atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space);
75452167a2794c3 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost 2021-07-08 463
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 464 /* now update descriptor */
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 465 WRITE_ONCE(desc->tail, tail);
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 466
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 467 return 0;
4c22abfbcb8456d drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2020-01-20 468
4c22abfbcb8456d drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2020-01-20 @469 corrupted:
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 470 CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 471 desc->head, desc->tail, desc->status);
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2021-06-15 472 ctb->broken = true;
4c22abfbcb8456d drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 2020-01-20 473 return -EPIPE;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 474 }
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c Michal Wajdeczko 2017-05-26 475
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index de89d40abd38d..18af99a802f64 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -379,8 +379,10 @@ static int ct_write(struct intel_guc_ct *ct, u32 *cmds = ctb->cmds; unsigned int i; +#ifdef CONFIG_DRM_I915_DEBUG_GUC if (unlikely(desc->status)) goto corrupted; +#endif GEM_BUG_ON(tail > size); @@ -815,8 +817,10 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (unlikely(ctb->broken)) return -EPIPE; +#ifdef CONFIG_DRM_I915_DEBUG_GUC if (unlikely(desc->status)) goto corrupted; +#endif GEM_BUG_ON(head > size);
Don't check CT descriptor status, unless CONFIG_DRM_I915_DEBUG_GUC is set, before CT write / read as this could result in a read across the PCIe bus thus adding latency to every CT write / read. On well behavied systems this vaue should always read as zero. For some reason it doesn't the CT channel is broken and will eventually recover from a GT reset, albeit the GT reset will not be triggered immediately by seeing that descriptor status is non-zero. Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 ++++ 1 file changed, 4 insertions(+)