From patchwork Fri Mar 4 17:23:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12769579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B080C433FE for ; Fri, 4 Mar 2022 17:24:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DAB41129CE; Fri, 4 Mar 2022 17:24:26 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id A733F112A32; Fri, 4 Mar 2022 17:24:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646414664; x=1677950664; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LKGc1TT9GPmDXb9i3/Z6KC6MlQAG3xUDW2WIV92/s50=; b=mDgOH3SWSQRCMTgpPJNkHvGTVp3DnTUKliqg3+xIYM3+KUe3Abkql22i fn1MwzeYmLbqAH8+DbL9dwNkRWowm6RFdZ40UFZpiTEDYRIB/BCURCZBc GaItbomHrnkIqbHObyMQYhjw2rxMvZa5Fh0DJMrIjy69iB+vEkvVsJ722 cncY4D7onG6M2eExsqgyhjpDOuvns6qeg3s+QulY0bQoANA1lXyRVpi2d RzNBZsxV61U9vc2eYcv8ruNajPqUtmzOxO9EHSy5d7eXWpwKTc/cC5mN0 C4iKyUUzSdwPnteCLaTD2FtmSaFvU7XA41hktvE7fQbZr/iNehA7zA35w g==; X-IronPort-AV: E=McAfee;i="6200,9189,10276"; a="252848990" X-IronPort-AV: E=Sophos;i="5.90,155,1643702400"; d="scan'208";a="252848990" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2022 09:24:24 -0800 X-IronPort-AV: E=Sophos;i="5.90,155,1643702400"; d="scan'208";a="631216631" Received: from vkats-mobl1.ccr.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.252.28.8]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2022 09:24:23 -0800 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Subject: [PATCH 7/8] drm/i915: fixup the initial fb base on DG1 Date: Fri, 4 Mar 2022 17:23:32 +0000 Message-Id: <20220304172333.991778-8-matthew.auld@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220304172333.991778-1-matthew.auld@intel.com> References: <20220304172333.991778-1-matthew.auld@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The offset we get looks to be the exact start of DSM, but the inital_plane_vma expects the address to be relative. Signed-off-by: Matthew Auld Cc: Thomas Hellström --- .../drm/i915/display/intel_plane_initial.c | 22 +++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c index f797fcef18fc..b39d3a8dfe45 100644 --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c @@ -56,10 +56,24 @@ initial_plane_vma(struct drm_i915_private *i915, if (!mem || plane_config->size == 0) return NULL; - base = round_down(plane_config->base, - I915_GTT_MIN_ALIGNMENT); - size = round_up(plane_config->base + plane_config->size, - mem->min_page_size); + base = plane_config->base; + if (IS_DGFX(i915)) { + /* + * On discrete the base address should be somewhere in LMEM, but + * depending on the size of LMEM the base address might + * intersect with the start of DSM, like on DG1, in which case + * we need the relative address. In such cases we might also + * need to choose between inital fb vs fbc, if space is limited. + * + * On future discrete HW, like DG2, we should be able to just + * allocate directly from LMEM, due to larger LMEM size. + */ + if (base >= i915->dsm.start) + base -= i915->dsm.start; + } + + size = roundup(base + plane_config->size, mem->min_page_size); + base = round_down(base, I915_GTT_MIN_ALIGNMENT); size -= base; /*