From patchwork Thu Mar 10 12:27:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12776277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC6D0C433F5 for ; Thu, 10 Mar 2022 12:28:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AEF0910EAB2; Thu, 10 Mar 2022 12:28:29 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 432F210EA9D; Thu, 10 Mar 2022 12:28:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646915308; x=1678451308; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2Gwec4q2cDKHyNIkCz+6Fl23U8jm8YNf66wvC8Un4Y0=; b=FoLfTL5EJ0r4PQ4aa2VkWMXbvq3xDkbTGhT/l1mdBX5cHM6jY7qUpVDt vCZiOqN2CrZMKq/t0v9GEviavVnDa46Odxkh3txtzOwrLoTAmn8afSe/i H5e3UFiHHEM32dA3UxzXNs0zPAPE/RE9YLv1w1soKYQPnO/N0JKZe8+Dw BiICpnHrG3KksG2G7B1HexDqFwwj1JDnf6gWKaiXiwvdP2ujp4seJ9pM5 VqxmjX/uEAib/Q3bpT+L01Hz3CR6oyeTmDYNpAebCDvyQC4yhsKHBQrhl HDkt0wmSqULOjxMfmb8k9+TNgHB3n9LS3HP2GuZxAvX+WV3AYm4m/YTGT g==; X-IronPort-AV: E=McAfee;i="6200,9189,10281"; a="341665172" X-IronPort-AV: E=Sophos;i="5.90,170,1643702400"; d="scan'208";a="341665172" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 04:28:28 -0800 X-IronPort-AV: E=Sophos;i="5.90,170,1643702400"; d="scan'208";a="496237743" Received: from tcuddihy-mobl.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.252.3.1]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 04:28:25 -0800 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 6/8] drm/i915/display: Check mappable aperture when pinning preallocated vma Date: Thu, 10 Mar 2022 12:27:49 +0000 Message-Id: <20220310122751.89693-7-matthew.auld@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220310122751.89693-1-matthew.auld@intel.com> References: <20220310122751.89693-1-matthew.auld@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Radhakrishna Sripada , Ap Kamal , Chris P Wilson , CQ Tang , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: CQ Tang When system does not have mappable aperture, ggtt->mappable_end=0. In this case if we pass PIN_MAPPABLE when pinning vma, the pinning code will return -ENOSPC. So conditionally set PIN_MAPPABLE if HAS_GMCH(). Suggested-by: Chris P Wilson Signed-off-by: CQ Tang Cc: Radhakrishna Sripada Cc: Ap Kamal Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Ville Syrjälä Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/display/intel_plane_initial.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c index 5227e5b35206..f797fcef18fc 100644 --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c @@ -51,6 +51,7 @@ initial_plane_vma(struct drm_i915_private *i915, struct drm_i915_gem_object *obj; struct i915_vma *vma; u32 base, size; + u64 pinctl; if (!mem || plane_config->size == 0) return NULL; @@ -101,7 +102,10 @@ initial_plane_vma(struct drm_i915_private *i915, if (IS_ERR(vma)) goto err_obj; - if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base)) + pinctl = PIN_GLOBAL | PIN_OFFSET_FIXED | base; + if (HAS_GMCH(i915)) + pinctl |= PIN_MAPPABLE; + if (i915_vma_pin(vma, 0, 0, pinctl)) goto err_obj; if (i915_gem_object_is_tiled(obj) &&