From patchwork Mon May 2 11:10:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 12834119 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C55DBC433F5 for ; Mon, 2 May 2022 11:09:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 73BE110E2B7; Mon, 2 May 2022 11:09:23 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 94F0D10E2B7; Mon, 2 May 2022 11:09:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651489762; x=1683025762; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ARiI9LiT9mXlYxlDFe5o6IuvjFJuwXY1uWR8sx85VUY=; b=UTmhHWOgqWGBYd+zJaDcePqDpJbNmjP5vJ+mupmxdfQZ1gqYXMGZdfeh +eBco6xrPDBY/lmHDT/jhZgvJfNViuS+suEWW9MbnnsomYK5szcwjKPWc ghgu3UXC4K0/R1d9A3uKyB3EMPZCqoMGT1yIAne1/3Ll6f+aeuRfGlo9o 7Gdh9E8YyTZq/v/ERmZ7xQ12Yg6VEyMwzI6QiN9im2/JEML4UX87uqieD Pvtex4c/Jl5EeyJZ2MlDgk4i4bR1cAcsnsF4jCt5b0W153VgithrpsaKh xVsx6kbL1FudXSSuqJPnIxs58YlB2GnWXeIB1z5xM4F4u3BuzsDNhICRp A==; X-IronPort-AV: E=McAfee;i="6400,9594,10334"; a="254632181" X-IronPort-AV: E=Sophos;i="5.91,190,1647327600"; d="scan'208";a="254632181" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2022 04:09:12 -0700 X-IronPort-AV: E=Sophos;i="5.91,190,1647327600"; d="scan'208";a="535800156" Received: from ramaling-i9x.iind.intel.com ([10.203.144.108]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2022 04:09:10 -0700 From: Ramalingam C To: intel-gfx , dri-devel Subject: [PATCH v4 4/4] drm/i915/selftest: Clear the output buffers before GPU writes Date: Mon, 2 May 2022 16:40:03 +0530 Message-Id: <20220502111003.32397-5-ramalingam.c@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220502111003.32397-1-ramalingam.c@intel.com> References: <20220502111003.32397-1-ramalingam.c@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Hellstrom , Chris Wilson , CQ Tang , Hellstrom Thomas Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chris Wilson When testing whether we can get the GPU to leak information about non-privileged state, we first need to ensure that the output buffer is set to a known value as the HW may opt to skip the write into memory for a non-privileged read of a sensitive register. We chose POISON_INUSE (0x5a) so that is both non-zero and distinct from the poison values used during the test. v2: Use i915_gem_object_pin_map_unlocked Reported-by: CQ Tang Signed-off-by: Chris Wilson Cc: CQ Tang cc: Joonas Lahtinen Signed-off-by: Ramalingam C Reviewed-by: Thomas Hellstrom --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 32 ++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index e4d5d74489bf..d04d08d9d92e 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -1395,6 +1395,30 @@ static int compare_isolation(struct intel_engine_cs *engine, return err; } +static struct i915_vma * +create_result_vma(struct i915_address_space *vm, unsigned long sz) +{ + struct i915_vma *vma; + void *ptr; + + vma = create_user_vma(vm, sz); + if (IS_ERR(vma)) + return vma; + + /* Set the results to a known value distinct from the poison */ + ptr = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC); + if (IS_ERR(ptr)) { + i915_vma_put(vma); + return ERR_CAST(ptr); + } + + memset(ptr, POISON_INUSE, vma->size); + i915_gem_object_flush_map(vma->obj); + i915_gem_object_unpin_map(vma->obj); + + return vma; +} + static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison) { u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1); @@ -1413,13 +1437,13 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison) goto err_A; } - ref[0] = create_user_vma(A->vm, SZ_64K); + ref[0] = create_result_vma(A->vm, SZ_64K); if (IS_ERR(ref[0])) { err = PTR_ERR(ref[0]); goto err_B; } - ref[1] = create_user_vma(A->vm, SZ_64K); + ref[1] = create_result_vma(A->vm, SZ_64K); if (IS_ERR(ref[1])) { err = PTR_ERR(ref[1]); goto err_ref0; @@ -1441,13 +1465,13 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison) } i915_request_put(rq); - result[0] = create_user_vma(A->vm, SZ_64K); + result[0] = create_result_vma(A->vm, SZ_64K); if (IS_ERR(result[0])) { err = PTR_ERR(result[0]); goto err_ref1; } - result[1] = create_user_vma(A->vm, SZ_64K); + result[1] = create_result_vma(A->vm, SZ_64K); if (IS_ERR(result[1])) { err = PTR_ERR(result[1]); goto err_result0;