| Message ID | 20220516100213.1536571-4-cyndis@kapsi.fi (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Host1x support on Tegra234 | expand |
On 16/05/2022 12:02, cyndis@kapsi.fi wrote: > From: Mikko Perttunen <mperttunen@nvidia.com> > > Add device tree nodes for Host1x and VIC on Tegra234. > > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > --- > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 46 ++++++++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > index cb3af539e477..cae68e59580c 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > @@ -454,6 +454,52 @@ misc@100000 { > status = "okay"; > }; > > + host1x@13e00000 { Generic node names, if that possible. Since the bindings do not exist in the next, I actually cannot figure out what's host1x... > + compatible = "nvidia,tegra234-host1x"; > + reg = <0x13e00000 0x10000>, > + <0x13e10000 0x10000>, > + <0x13e40000 0x10000>; > + reg-names = "common", "hypervisor", "vm"; > + interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", > + "syncpt5", "syncpt6", "syncpt7", "host1x"; > + clocks = <&bpmp TEGRA234_CLK_HOST1X>; > + clock-names = "host1x"; > + > + #address-cells = <1>; > + #size-cells = <1>; > + > + ranges = <0x15000000 0x15000000 0x01000000>; > + interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; > + interconnect-names = "dma-mem"; > + iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; > + > + vic@15340000 { The same... vic is usually a vectored interrupt controller, so this should be interrupt-controller. Unless it is something entirely else, so then you need to come with a generic name. Best regards, Krzysztof
On 5/17/22 11:01, Krzysztof Kozlowski wrote: > On 16/05/2022 12:02, cyndis@kapsi.fi wrote: >> From: Mikko Perttunen <mperttunen@nvidia.com> >> >> Add device tree nodes for Host1x and VIC on Tegra234. >> >> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> >> --- >> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 46 ++++++++++++++++++++++++ >> 1 file changed, 46 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi >> index cb3af539e477..cae68e59580c 100644 >> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi >> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi >> @@ -454,6 +454,52 @@ misc@100000 { >> status = "okay"; >> }; >> >> + host1x@13e00000 { > > Generic node names, if that possible. Since the bindings do not exist in > the next, I actually cannot figure out what's host1x... Host1x is a hardware block that provides programmable DMA channels, HW synchronization primitives, and virtualization support for IP blocks connected to its "host1x bus". So far I haven't found a one or two word way to describe it despite efforts. In any case, considering all the existing documentation and device trees that use this name, I'd prefer not changing it (especially as I don't know what else it could be called). > >> + compatible = "nvidia,tegra234-host1x"; >> + reg = <0x13e00000 0x10000>, >> + <0x13e10000 0x10000>, >> + <0x13e40000 0x10000>; >> + reg-names = "common", "hypervisor", "vm"; >> + interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", >> + "syncpt5", "syncpt6", "syncpt7", "host1x"; >> + clocks = <&bpmp TEGRA234_CLK_HOST1X>; >> + clock-names = "host1x"; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + ranges = <0x15000000 0x15000000 0x01000000>; >> + interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; >> + interconnect-names = "dma-mem"; >> + iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; >> + >> + vic@15340000 { > > The same... vic is usually a vectored interrupt controller, so this > should be interrupt-controller. Unless it is something entirely else, so > then you need to come with a generic name. VIC here is video image compositor (with various other 2d operations). I suppose I can invent some generic name. Any thoughts, Thierry? Mikko > > > Best regards, > Krzysztof
On 17/05/2022 10:38, Mikko Perttunen wrote: >>> >>> + host1x@13e00000 { >> >> Generic node names, if that possible. Since the bindings do not exist in >> the next, I actually cannot figure out what's host1x... > > Host1x is a hardware block that provides programmable DMA channels, HW > synchronization primitives, and virtualization support for IP blocks > connected to its "host1x bus". So far I haven't found a one or two word > way to describe it despite efforts. In any case, considering all the > existing documentation and device trees that use this name, I'd prefer > not changing it (especially as I don't know what else it could be called). OK Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index cb3af539e477..cae68e59580c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -454,6 +454,52 @@ misc@100000 { status = "okay"; }; + host1x@13e00000 { + compatible = "nvidia,tegra234-host1x"; + reg = <0x13e00000 0x10000>, + <0x13e10000 0x10000>, + <0x13e40000 0x10000>; + reg-names = "common", "hypervisor", "vm"; + interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", + "syncpt5", "syncpt6", "syncpt7", "host1x"; + clocks = <&bpmp TEGRA234_CLK_HOST1X>; + clock-names = "host1x"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x15000000 0x15000000 0x01000000>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; + interconnect-names = "dma-mem"; + iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; + + vic@15340000 { + compatible = "nvidia,tegra234-vic"; + reg = <0x15340000 0x00040000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA234_CLK_VIC>; + clock-names = "vic"; + resets = <&bpmp TEGRA234_RESET_VIC>; + reset-names = "vic"; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_VIC>; + dma-coherent; + }; + }; + gpio: gpio@2200000 { compatible = "nvidia,tegra234-gpio"; reg-names = "security", "gpio";