diff mbox series

drm/i915: Add global forcewake status to drpc

Message ID 20220617202534.30609-1-vinay.belgaumkar@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Add global forcewake status to drpc | expand

Commit Message

Vinay Belgaumkar June 17, 2022, 8:25 p.m. UTC 
We have seen multiple RC6 issues where it is useful to know
which global forcewake bits are set. Add this to the 'drpc'
debugfs output.

Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

Comments

Dixit, Ashutosh June 17, 2022, 8:53 p.m. UTC | #1 
On Fri, 17 Jun 2022 13:25:34 -0700, Vinay Belgaumkar wrote:
>
> We have seen multiple RC6 issues where it is useful to know
> which global forcewake bits are set. Add this to the 'drpc'
> debugfs output.

A couple of optional nits below to look at but otherwise this is:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

> +static u32 mt_fwake_status(struct intel_uncore *uncore)
> +{
> +	return intel_uncore_read_fw(uncore, FORCEWAKE_MT);
> +}
> +
>  static int vlv_drpc(struct seq_file *m)
>  {
>	struct intel_gt *gt = m->private;
>	struct intel_uncore *uncore = gt->uncore;
> -	u32 rcctl1, pw_status;
> +	u32 rcctl1, pw_status, mt_fwake;
>
> +	mt_fwake = mt_fwake_status(uncore);

I would get rid of the function and just duplicate the intel_uncore_read_fw().

>	pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS);
>	rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
>
>	seq_printf(m, "RC6 Enabled: %s\n",
>		   str_yes_no(rcctl1 & (GEN7_RC_CTL_TO_MODE |
>					GEN6_RC_CTL_EI_MODE(1))));
> +	seq_printf(m, "Multi-threaded Forcewake: 0x%x\n", mt_fwake);

Is "Multi-threaded Forcewake Request" (the Bspec register name) a more
descriptive print?

Same for gen6_drpc() below. Thanks!
Vinay Belgaumkar June 17, 2022, 9:11 p.m. UTC | #2 
On 6/17/2022 1:53 PM, Dixit, Ashutosh wrote:
> On Fri, 17 Jun 2022 13:25:34 -0700, Vinay Belgaumkar wrote:
>> We have seen multiple RC6 issues where it is useful to know
>> which global forcewake bits are set. Add this to the 'drpc'
>> debugfs output.
> A couple of optional nits below to look at but otherwise this is:
>
> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>
>> +static u32 mt_fwake_status(struct intel_uncore *uncore)
>> +{
>> +	return intel_uncore_read_fw(uncore, FORCEWAKE_MT);
>> +}
>> +
>>   static int vlv_drpc(struct seq_file *m)
>>   {
>> 	struct intel_gt *gt = m->private;
>> 	struct intel_uncore *uncore = gt->uncore;
>> -	u32 rcctl1, pw_status;
>> +	u32 rcctl1, pw_status, mt_fwake;
>>
>> +	mt_fwake = mt_fwake_status(uncore);
> I would get rid of the function and just duplicate the intel_uncore_read_fw().
Made it a function in case we can find the equivalent register for ILK. 
Though, I am not sure if ILK even had the concept of MT fwake.
>
>> 	pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS);
>> 	rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
>>
>> 	seq_printf(m, "RC6 Enabled: %s\n",
>> 		   str_yes_no(rcctl1 & (GEN7_RC_CTL_TO_MODE |
>> 					GEN6_RC_CTL_EI_MODE(1))));
>> +	seq_printf(m, "Multi-threaded Forcewake: 0x%x\n", mt_fwake);
> Is "Multi-threaded Forcewake Request" (the Bspec register name) a more
> descriptive print?
>
> Same for gen6_drpc() below. Thanks!

Sure.

Thanks,

Vinay.
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 90a440865037..2a157ca28dda 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -96,18 +96,25 @@  static void print_rc6_res(struct seq_file *m,
 			   intel_rc6_residency_us(&gt->rc6, reg));
 }
 
+static u32 mt_fwake_status(struct intel_uncore *uncore)
+{
+	return intel_uncore_read_fw(uncore, FORCEWAKE_MT);
+}
+
 static int vlv_drpc(struct seq_file *m)
 {
 	struct intel_gt *gt = m->private;
 	struct intel_uncore *uncore = gt->uncore;
-	u32 rcctl1, pw_status;
+	u32 rcctl1, pw_status, mt_fwake;
 
+	mt_fwake = mt_fwake_status(uncore);
 	pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS);
 	rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
 
 	seq_printf(m, "RC6 Enabled: %s\n",
 		   str_yes_no(rcctl1 & (GEN7_RC_CTL_TO_MODE |
 					GEN6_RC_CTL_EI_MODE(1))));
+	seq_printf(m, "Multi-threaded Forcewake: 0x%x\n", mt_fwake);
 	seq_printf(m, "Render Power Well: %s\n",
 		   (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
 	seq_printf(m, "Media Power Well: %s\n",
@@ -124,9 +131,10 @@  static int gen6_drpc(struct seq_file *m)
 	struct intel_gt *gt = m->private;
 	struct drm_i915_private *i915 = gt->i915;
 	struct intel_uncore *uncore = gt->uncore;
-	u32 gt_core_status, rcctl1, rc6vids = 0;
+	u32 gt_core_status, mt_fwake, rcctl1, rc6vids = 0;
 	u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
 
+	mt_fwake = mt_fwake_status(uncore);
 	gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
 
 	rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
@@ -178,6 +186,7 @@  static int gen6_drpc(struct seq_file *m)
 
 	seq_printf(m, "Core Power Down: %s\n",
 		   str_yes_no(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
+	seq_printf(m, "Multi-threaded Forcewake: 0x%x\n", mt_fwake);
 	if (GRAPHICS_VER(i915) >= 9) {
 		seq_printf(m, "Render Power Well: %s\n",
 			   (gen9_powergate_status &