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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id m1-20020a7bcb81000000b003a05621dc53sm6286532wmi.29.2022.06.30.05.08.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jun 2022 05:08:55 -0700 (PDT) From: Bryan O'Donoghue To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH 6/7] dt-bindings: msm: dsi: Add missing clocks to 28nm DSI PHY YAML Date: Thu, 30 Jun 2022 13:08:44 +0100 Message-Id: <20220630120845.3356144-7-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220630120845.3356144-1-bryan.odonoghue@linaro.org> References: <20220630120845.3356144-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 01 Jul 2022 07:33:24 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, bjorn.andersson@linaro.org, quic_mkrishn@quicinc.com, bryan.odonoghue@linaro.org, swboyd@chromium.org, freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add in missing clock and clock-names declarations to the 28nm DSI PHY. When converting from .txt to .yaml we missed these. Fixes: 4dbe55c97741 ("dt-bindings: msm: dsi: add yaml schemas for DSI bindings") Signed-off-by: Bryan O'Donoghue --- .../bindings/display/msm/dsi-phy-28nm.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml index 3d8540a06fe22..9ecd513d93661 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml @@ -19,6 +19,21 @@ properties: - qcom,dsi-phy-28nm-lp - qcom,dsi-phy-28nm-8960 + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + items: + - const: iface + description: AHB clock + - const: iface_clk + description: AHB clock + - const: ref + description: Block reference clock + minItems: 1 + maxItems: 2 + reg: items: - description: dsi pll register set @@ -36,6 +51,8 @@ properties: required: - compatible + - clocks + - clock-names - reg - reg-names - vddio-supply