From patchwork Fri Jul 1 22:50:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niranjana Vishwanathapura X-Patchwork-Id: 12903835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89369CCA479 for ; Fri, 1 Jul 2022 22:51:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A8FD21125AC; Fri, 1 Jul 2022 22:51:20 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 774BE11255E; Fri, 1 Jul 2022 22:51:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656715878; x=1688251878; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+3xnT/DIafDuGtQ2Xs+GzzEU4YW0wN0G12hQGxxIU3k=; b=Tka+C1mQVDG6py9CjgIaLga748ET4wd83A5CkaYeNQEW62D/+Hb0aJYc KCOSDJ2JYKcdHqC4ELbDEKRo9j+8+dja9K1VFkonmUC9nzkMBbdH5URRG 6wVJ586MS4GIwPXuQ4qpBGFGqTtRkV+albSLHh+gi55V5+fEU7VqxkSEl ZXnpWFKTfXp5ZNcH9ZwKqwWjXe5RvGZfQ8sRSBjHl8AY0aWiLGlCKSe5Q l40SzQ9+nANpUS3PfgQZDc2pgSgyal5NKEgYW6eFUcsXjOQTnnRWWIu7p VGdXWxeCNaE4hZYte2BrXadnzP4rh6W8xaIYUSYO7Et/frsQ8gEqJOeFa Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10395"; a="282789050" X-IronPort-AV: E=Sophos;i="5.92,238,1650956400"; d="scan'208";a="282789050" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2022 15:51:17 -0700 X-IronPort-AV: E=Sophos;i="5.92,238,1650956400"; d="scan'208";a="918645096" Received: from nvishwa1-desk.sc.intel.com ([172.25.29.76]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 01 Jul 2022 15:51:17 -0700 From: Niranjana Vishwanathapura To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 04/10] drm/i915/vm_bind: Add out fence support Date: Fri, 1 Jul 2022 15:50:49 -0700 Message-Id: <20220701225055.8204-5-niranjana.vishwanathapura@intel.com> X-Mailer: git-send-email 2.21.0.rc0.32.g243a4c7e27 In-Reply-To: <20220701225055.8204-1-niranjana.vishwanathapura@intel.com> References: <20220701225055.8204-1-niranjana.vishwanathapura@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, lionel.g.landwerlin@intel.com, thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, daniel.vetter@intel.com, christian.koenig@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for handling out fence of vm_bind call. Signed-off-by: Niranjana Vishwanathapura --- drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | 2 + .../drm/i915/gem/i915_gem_vm_bind_object.c | 74 +++++++++++++++++++ drivers/gpu/drm/i915/i915_vma.c | 6 +- drivers/gpu/drm/i915/i915_vma_types.h | 7 ++ 4 files changed, 88 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h index ee6e4c52e80e..849bf3c1061e 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h @@ -45,5 +45,7 @@ int i915_gem_vm_bind_obj(struct i915_address_space *vm, struct drm_file *file); int i915_gem_vm_unbind_obj(struct i915_address_space *vm, struct drm_i915_gem_vm_unbind *va); +void i915_vm_bind_signal_fence(struct i915_vma *vma, + struct dma_fence * const fence); #endif /* __I915_GEM_VM_BIND_H */ diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c index 3201204c8e74..96f139cc8060 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c @@ -5,6 +5,8 @@ #include +#include + #include "gem/i915_gem_vm_bind.h" #include "gt/gen8_engine_cs.h" @@ -94,6 +96,68 @@ void i915_gem_vm_bind_remove(struct i915_vma *vma, bool release_obj) } } +static int i915_vm_bind_add_fence(struct drm_file *file, struct i915_vma *vma, + u32 handle, u64 point) +{ + struct drm_syncobj *syncobj; + + syncobj = drm_syncobj_find(file, handle); + if (!syncobj) { + DRM_DEBUG("Invalid syncobj handle provided\n"); + return -ENOENT; + } + + /* + * For timeline syncobjs we need to preallocate chains for + * later signaling. + */ + if (point) { + vma->vm_bind_fence.chain_fence = dma_fence_chain_alloc(); + if (!vma->vm_bind_fence.chain_fence) { + drm_syncobj_put(syncobj); + return -ENOMEM; + } + } else { + vma->vm_bind_fence.chain_fence = NULL; + } + + vma->vm_bind_fence.syncobj = syncobj; + vma->vm_bind_fence.value = point; + + return 0; +} + +static void i915_vm_bind_put_fence(struct i915_vma *vma) +{ + if (!vma->vm_bind_fence.syncobj) + return; + + drm_syncobj_put(vma->vm_bind_fence.syncobj); + dma_fence_chain_free(vma->vm_bind_fence.chain_fence); +} + +void i915_vm_bind_signal_fence(struct i915_vma *vma, + struct dma_fence * const fence) +{ + struct drm_syncobj *syncobj = vma->vm_bind_fence.syncobj; + + if (!syncobj) + return; + + if (vma->vm_bind_fence.chain_fence) { + drm_syncobj_add_point(syncobj, + vma->vm_bind_fence.chain_fence, + fence, vma->vm_bind_fence.value); + /* + * The chain's ownership is transferred to the + * timeline. + */ + vma->vm_bind_fence.chain_fence = NULL; + } else { + drm_syncobj_replace_fence(syncobj, fence); + } +} + int i915_gem_vm_unbind_obj(struct i915_address_space *vm, struct drm_i915_gem_vm_unbind *va) { @@ -202,6 +266,14 @@ int i915_gem_vm_bind_obj(struct i915_address_space *vm, } i915_gem_ww_ctx_init(&ww, true); + + if (va->fence.flags & I915_TIMELINE_FENCE_SIGNAL) { + ret = i915_vm_bind_add_fence(file, vma, va->fence.handle, + va->fence.value); + if (ret) + goto put_vma; + } + pin_flags = va->start | PIN_OFFSET_FIXED | PIN_USER; retry: ret = i915_gem_object_lock(vma->obj, &ww); @@ -230,6 +302,8 @@ int i915_gem_vm_bind_obj(struct i915_address_space *vm, goto retry; } + i915_vm_bind_put_fence(vma); +put_vma: if (ret) i915_vma_destroy(vma); diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index f0226581d342..6737236b7884 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -1510,8 +1510,12 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, err_vma_res: i915_vma_resource_free(vma_res); err_fence: - if (work) + if (work) { + if (i915_vma_is_persistent(vma)) + i915_vm_bind_signal_fence(vma, &work->base.dma); + dma_fence_work_commit_imm(&work->base); + } err_rpm: if (wakeref) intel_runtime_pm_put(&vma->vm->i915->runtime_pm, wakeref); diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h index 2298b3d6b7c4..7d830a6a0b51 100644 --- a/drivers/gpu/drm/i915/i915_vma_types.h +++ b/drivers/gpu/drm/i915/i915_vma_types.h @@ -293,6 +293,13 @@ struct i915_vma { /* Link in non-private persistent VMA list */ struct list_head non_priv_vm_bind_link; + /** Timeline fence for vm_bind completion notification */ + struct { + struct drm_syncobj *syncobj; + u64 value; + struct dma_fence_chain *chain_fence; + } vm_bind_fence; + /** Interval tree structures for persistent vma */ struct rb_node rb; u64 start;