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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id g34-20020a05600c4ca200b0039c7dbafa7asm18353920wmp.19.2022.07.05.14.52.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jul 2022 14:52:29 -0700 (PDT) From: Conor Dooley To: David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Thierry Reding , Sam Ravnborg , Eugeniy Paltsev , Vinod Koul , Serge Semin , Daniel Lezcano , Palmer Dabbelt , Palmer Dabbelt Subject: [PATCH v5 04/13] dt-bindings: memory-controllers: add canaan k210 sram controller Date: Tue, 5 Jul 2022 22:52:05 +0100 Message-Id: <20220705215213.1802496-5-mail@conchuod.ie> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220705215213.1802496-1-mail@conchuod.ie> References: <20220705215213.1802496-1-mail@conchuod.ie> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Niklas Cassel , Albert Ou , devicetree@vger.kernel.org, Damien Le Moal , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Conor Dooley , Geert Uytterhoeven , Paul Walmsley , dmaengine@vger.kernel.org, linux-riscv@lists.infradead.org, Dillon Min , Masahiro Yamada Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Conor Dooley The k210 U-Boot port has been using the clocks defined in the devicetree to bring up the board's SRAM, but this violates the dt-schema. As such, move the clocks to a dedicated node with the same compatible string & document it. Signed-off-by: Conor Dooley Reviewed-by: Rob Herring Reviewed-by: Krzysztof Kozlowski --- .../memory-controllers/canaan,k210-sram.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml b/Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml new file mode 100644 index 000000000000..f81fb866e319 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/canaan,k210-sram.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan K210 SRAM memory controller + +description: + The Canaan K210 SRAM memory controller is responsible for the system's 8 MiB + of SRAM. The controller is initialised by the bootloader, which configures + its clocks, before OS bringup. + +maintainers: + - Conor Dooley + +properties: + compatible: + enum: + - canaan,k210-sram + + clocks: + minItems: 1 + items: + - description: sram0 clock + - description: sram1 clock + - description: aisram clock + + clock-names: + minItems: 1 + items: + - const: sram0 + - const: sram1 + - const: aisram + +required: + - compatible + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + memory-controller { + compatible = "canaan,k210-sram"; + clocks = <&sysclk K210_CLK_SRAM0>, + <&sysclk K210_CLK_SRAM1>, + <&sysclk K210_CLK_AI>; + clock-names = "sram0", "sram1", "aisram"; + };