From patchwork Fri Jul 22 20:33:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Almeida?= X-Patchwork-Id: 12926883 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9AB4C433EF for ; Fri, 22 Jul 2022 20:34:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A86C793B63; Fri, 22 Jul 2022 20:34:30 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine.igalia.com [178.60.130.6]) by gabe.freedesktop.org (Postfix) with ESMTPS id 095CE93B5D; Fri, 22 Jul 2022 20:34:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=TH9rxss53zay8H/y7PCgnrx83MHhoOnTSfGz46xB6jE=; b=SQO0yqwM5M+h50J1oBwTsZbqG9 qNSvreEVeIreCuyRknn52tOS5WFJ/2S7TFJjGOA4ZRo6wsiCJaCZsUo2IOnIx4DNj5SiERDPRrboe rTNB+ooxIhggBhwlInkrNgtfcJ+CR+gUEvc+E4rrhhrOkFATPXJyVmwLAe4NESC+qquMPK74AsOu3 rfWsa3p9QO5KZsbL2DogGXrY4JeJAmnuK6bx+HP5ONkIlqy9PsR2aDnWogXPSu2M+hnSO5dDDeObQ vny/46ZNxe97H1PJlQzQyNqGTCw8tFfuIvdE7G1YI46YmtIHCT7acN+t7qO7S4Teht2HXY+a5sH4a 1vjXtxKg==; Received: from 201-13-50-220.dsl.telesp.net.br ([201.13.50.220] helo=localhost.localdomain) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1oEzLt-002fLB-Qo; Fri, 22 Jul 2022 22:34:26 +0200 From: =?utf-8?q?Andr=C3=A9_Almeida?= To: Alex Deucher , =?utf-8?b?J0NocmlzdGlhbiBLw7Zu?= =?utf-8?b?aWcn?= , 'Pan Xinhui' , David Airlie , Daniel Vetter , Hawking Zhang , Tao Zhou , Felix Kuehling , Jack Xiao , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tom St Denis , Rodrigo Siqueira Subject: [PATCH 2/4] drm/amd/pm: Implement GFXOFF's entry count and residency for vangogh Date: Fri, 22 Jul 2022 17:33:45 -0300 Message-Id: <20220722203347.70176-3-andrealmeid@igalia.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220722203347.70176-1-andrealmeid@igalia.com> References: <20220722203347.70176-1-andrealmeid@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Andr=C3=A9_Almeida?= , kernel-dev@igalia.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Implement functions to get and set GFXOFF's entry count and residency for vangogh. Signed-off-by: André Almeida --- .../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h | 5 +- drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 5 +- .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 92 +++++++++++++++++++ 3 files changed, 100 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h index fe130a497d6c..7471e2df2828 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h @@ -108,7 +108,10 @@ #define PPSMC_MSG_SetSlowPPTLimit 0x4A #define PPSMC_MSG_GetFastPPTLimit 0x4B #define PPSMC_MSG_GetSlowPPTLimit 0x4C -#define PPSMC_Message_Count 0x4D +#define PPSMC_MSG_GetGfxOffStatus 0x50 +#define PPSMC_MSG_GetGfxOffEntryCount 0x51 +#define PPSMC_MSG_LogGfxOffResidency 0x52 +#define PPSMC_Message_Count 0x53 //Argument for PPSMC_MSG_GfxDeviceDriverReset enum { diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index 19084a4fcb2b..76fb6cbbc09c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -235,7 +235,10 @@ __SMU_DUMMY_MAP(UnforceGfxVid), \ __SMU_DUMMY_MAP(HeavySBR), \ __SMU_DUMMY_MAP(SetBadHBMPagesRetiredFlagsPerChannel), \ - __SMU_DUMMY_MAP(EnableGfxImu), + __SMU_DUMMY_MAP(EnableGfxImu), \ + __SMU_DUMMY_MAP(GetGfxOffStatus), \ + __SMU_DUMMY_MAP(GetGfxOffEntryCount), \ + __SMU_DUMMY_MAP(LogGfxOffResidency), #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(type) SMU_MSG_##type diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 89504ff8e9ed..fff70f58a23c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -138,6 +138,9 @@ static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0), MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0), MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0), + MSG_MAP(GetGfxOffStatus, PPSMC_MSG_GetGfxOffStatus, 0), + MSG_MAP(GetGfxOffEntryCount, PPSMC_MSG_GetGfxOffEntryCount, 0), + MSG_MAP(LogGfxOffResidency, PPSMC_MSG_LogGfxOffResidency, 0), }; static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { @@ -2200,6 +2203,92 @@ static int vangogh_set_power_limit(struct smu_context *smu, return ret; } +/** + * vangogh_set_gfxoff_residency + * + * @smu: amdgpu_device pointer + * @start: start/stop residency log + * + * This function will be used to log gfxoff residency + * + * + * Returns standard response codes. + */ +static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start) +{ + int ret = 0; + u32 residency; + struct amdgpu_device *adev = smu->adev; + + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(11, 5, 0): + if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) + return 0; + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency, + start, &residency); + if (!start) + adev->gfx.gfx_off_residency = residency; + break; + default: + break; + } + + return ret; +} + +/** + * vangogh_get_gfxoff_residency + * + * @smu: amdgpu_device pointer + * + * This function will be used to get gfxoff residency. + * + * Returns standard response codes. + */ +static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency) +{ + int ret = 0; + struct amdgpu_device *adev = smu->adev; + + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(11, 5, 0): + *residency = adev->gfx.gfx_off_residency; + break; + default: + break; + } + + return ret; +} + +/** + * vangogh_get_gfxoff_entrycount - get gfxoff entry count + * + * @smu: amdgpu_device pointer + * + * This function will be used to get gfxoff entry count + * + * Returns standard response codes. + */ +static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint32_t *entrycount) +{ + int ret = 0; + struct amdgpu_device *adev = smu->adev; + + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(11, 5, 0): + if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) + return 0; + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, entrycount); + *entrycount += adev->gfx.gfx_off_entrycount; + break; + default: + break; + } + + return ret; +} + static const struct pptable_funcs vangogh_ppt_funcs = { .check_fw_status = smu_v11_0_check_fw_status, @@ -2237,6 +2326,9 @@ static const struct pptable_funcs vangogh_ppt_funcs = { .mode2_reset = vangogh_mode2_reset, .gfx_off_control = smu_v11_0_gfx_off_control, .get_gfx_off_status = vangogh_get_gfxoff_status, + .get_gfx_off_entrycount = vangogh_get_gfxoff_entrycount, + .get_gfx_off_residency = vangogh_get_gfxoff_residency, + .set_gfx_off_residency = vangogh_set_gfxoff_residency, .get_ppt_limit = vangogh_get_ppt_limit, .get_power_limit = vangogh_get_power_limit, .set_power_limit = vangogh_set_power_limit,