From patchwork Mon Jul 25 09:25:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gwan-gyeong Mun X-Patchwork-Id: 12927913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B3FAC43334 for ; Mon, 25 Jul 2022 09:26:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B963F18AABD; Mon, 25 Jul 2022 09:26:41 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4C4D02B454; Mon, 25 Jul 2022 09:26:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658741197; x=1690277197; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=krsjuX88+1+7otI9fGikp5c5oUC8wUFyY0WjsaIaF58=; b=CL1z9vhpEIe7+P71o/sE0MaNpxrRw29hDEeVcEZOm6Zc0G0Kr2tGxKgz NZRGXIUAz9dp246nZ4nmOmID0JHkZC2TTi+07m0Sn928SPLizx3ji9Cx3 AOsorF6X0/7GFt2CGa58QpHl+SoAZemyjkKra9M8IDLzynlxN7oNSFhhb EhDIXEoBWj7JngSzyJvm+uZwAR6755QzXSyXiFk+Y/cvLEIid58BAmVr/ IURSwYKwKBx14cZTYMwjZoKxmK3q8KlW0ThHDks70F8LfnsKI82sm2Xk0 zOy+h1+26tjOusrd10m5hnSTNkkEjUBMgJk/J7LRvU0YB6U2CE3nDSP6i A==; X-IronPort-AV: E=McAfee;i="6400,9594,10418"; a="268047815" X-IronPort-AV: E=Sophos;i="5.93,192,1654585200"; d="scan'208";a="268047815" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2022 02:26:30 -0700 X-IronPort-AV: E=Sophos;i="5.93,192,1654585200"; d="scan'208";a="926823848" Received: from abaruah-mobl.gar.corp.intel.com (HELO hades.ger.corp.intel.com) ([10.249.37.11]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2022 02:26:27 -0700 From: Gwan-gyeong Mun To: intel-gfx@lists.freedesktop.org Subject: [PATCH v5 4/7] drm/i915: Check for integer truncation on the configuration of ttm place Date: Mon, 25 Jul 2022 12:25:25 +0300 Message-Id: <20220725092528.1281487-5-gwan-gyeong.mun@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220725092528.1281487-1-gwan-gyeong.mun@intel.com> References: <20220725092528.1281487-1-gwan-gyeong.mun@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thomas.hellstrom@linux.intel.com, jani.nikula@intel.com, dri-devel@lists.freedesktop.org, chris@chris-wilson.co.uk, airlied@linux.ie, matthew.auld@intel.com, mchehab@kernel.org, nirmoy.das@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" There is an impedance mismatch between the first/last valid page frame number of ttm place in unsigned and our memory/page accounting in unsigned long. As the object size is under the control of userspace, we have to be prudent and catch the conversion errors. To catch the implicit truncation as we switch from unsigned long to unsigned, we use overflows_type check and report E2BIG or overflow_type prior to the operation. v3: Not to change execution inside a macro. (Mauro) Add safe_conversion_gem_bug_on() macro and remove temporal SAFE_CONVERSION() macro. v4: Fix unhandled GEM_BUG_ON() macro call from safe_conversion_gem_bug_on() Signed-off-by: Gwan-gyeong Mun Cc: Chris Wilson Cc: Matthew Auld Cc: Thomas Hellström Reviewed-by: Nirmoy Das Reviewed-by: Mauro Carvalho Chehab Reported-by: kernel test robot Reviewed-by: Andrzej Hajda --- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 6 +++--- drivers/gpu/drm/i915/i915_gem.h | 4 ++++ drivers/gpu/drm/i915/intel_region_ttm.c | 20 +++++++++++++++++--- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c index 9f2be1892b6c..88f2887627dc 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c @@ -140,14 +140,14 @@ i915_ttm_place_from_region(const struct intel_memory_region *mr, if (flags & I915_BO_ALLOC_CONTIGUOUS) place->flags |= TTM_PL_FLAG_CONTIGUOUS; if (offset != I915_BO_INVALID_OFFSET) { - place->fpfn = offset >> PAGE_SHIFT; - place->lpfn = place->fpfn + (size >> PAGE_SHIFT); + safe_conversion_gem_bug_on(&place->fpfn, offset >> PAGE_SHIFT); + safe_conversion_gem_bug_on(&place->lpfn, place->fpfn + (size >> PAGE_SHIFT)); } else if (mr->io_size && mr->io_size < mr->total) { if (flags & I915_BO_ALLOC_GPU_ONLY) { place->flags |= TTM_PL_FLAG_TOPDOWN; } else { place->fpfn = 0; - place->lpfn = mr->io_size >> PAGE_SHIFT; + safe_conversion_gem_bug_on(&place->lpfn, mr->io_size >> PAGE_SHIFT); } } } diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h index 68d8d52bd541..327dacedd5d1 100644 --- a/drivers/gpu/drm/i915/i915_gem.h +++ b/drivers/gpu/drm/i915/i915_gem.h @@ -83,5 +83,9 @@ struct drm_i915_private; #endif #define I915_GEM_IDLE_TIMEOUT (HZ / 5) +#define safe_conversion_gem_bug_on(ptr, value) !({ \ + safe_conversion(ptr, value) ? 0 \ + : (({ GEM_BUG_ON(overflows_type(value, *ptr)); }), 1); \ +}) #endif /* __I915_GEM_H__ */ diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c b/drivers/gpu/drm/i915/intel_region_ttm.c index 575d67bc6ffe..f0d143948725 100644 --- a/drivers/gpu/drm/i915/intel_region_ttm.c +++ b/drivers/gpu/drm/i915/intel_region_ttm.c @@ -209,14 +209,26 @@ intel_region_ttm_resource_alloc(struct intel_memory_region *mem, if (flags & I915_BO_ALLOC_CONTIGUOUS) place.flags |= TTM_PL_FLAG_CONTIGUOUS; if (offset != I915_BO_INVALID_OFFSET) { - place.fpfn = offset >> PAGE_SHIFT; - place.lpfn = place.fpfn + (size >> PAGE_SHIFT); + if (!safe_conversion_gem_bug_on(&place.fpfn, + offset >> PAGE_SHIFT)) { + ret = -E2BIG; + goto out; + } + if (!safe_conversion_gem_bug_on(&place.lpfn, + place.fpfn + (size >> PAGE_SHIFT))) { + ret = -E2BIG; + goto out; + } } else if (mem->io_size && mem->io_size < mem->total) { if (flags & I915_BO_ALLOC_GPU_ONLY) { place.flags |= TTM_PL_FLAG_TOPDOWN; } else { place.fpfn = 0; - place.lpfn = mem->io_size >> PAGE_SHIFT; + if (!safe_conversion_gem_bug_on(&place.lpfn, + mem->io_size >> PAGE_SHIFT)) { + ret = -E2BIG; + goto out; + } } } @@ -224,6 +236,8 @@ intel_region_ttm_resource_alloc(struct intel_memory_region *mem, mock_bo.bdev = &mem->i915->bdev; ret = man->func->alloc(man, &mock_bo, &place, &res); + +out: if (ret == -ENOSPC) ret = -ENXIO; if (!ret)