| Message ID | 20220801131555.182969-1-marex@denx.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm: bridge: icn6211: Add and use hs_rate and lp_rate | expand |
On Mon, Aug 1, 2022 at 3:16 PM Marek Vasut <marex@denx.de> wrote: > Fill in hs_rate and lp_rate to struct mipi_dsi_device for this bridge and > adjust DSI input frequency calculations such that they expect the DSI host > to configure HS clock according to hs_rate. > > This is an optimization for the DSI burst mode case. In case the DSI device > supports DSI burst mode, it is recommended to operate the DSI interface at > the highest possible HS clock frequency which the DSI device supports. This > permits the DSI host to send as short as possible bursts of data on the DSI > link and keep the DSI data lanes in LP mode otherwise, which reduces power > consumption. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Jagan Teki <jagan@amarulasolutions.com> > Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Cc: Linus Walleij <linus.walleij@linaro.org> > Cc: Robert Foss <robert.foss@linaro.org> > Cc: Sam Ravnborg <sam@ravnborg.org> > Cc: dri-devel@lists.freedesktop.org LGTM so patch applied to drm-misc-next Yours, Linus Walleij
diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c b/drivers/gpu/drm/bridge/chipone-icn6211.c index 481c86b2406e8..65966f280cf4e 100644 --- a/drivers/gpu/drm/bridge/chipone-icn6211.c +++ b/drivers/gpu/drm/bridge/chipone-icn6211.c @@ -259,7 +259,7 @@ static void chipone_configure_pll(struct chipone *icn, /* * DSI byte clock frequency (input into PLL) is calculated as: - * DSI_CLK = mode clock * bpp / dsi_data_lanes / 8 + * DSI_CLK = HS clock / 4 * * DPI pixel clock frequency (output from PLL) is mode clock. * @@ -273,8 +273,7 @@ static void chipone_configure_pll(struct chipone *icn, * It seems the PLL input clock after applying P pre-divider have * to be lower than 20 MHz. */ - fin = mode_clock * mipi_dsi_pixel_format_to_bpp(icn->dsi->format) / - icn->dsi->lanes / 8; /* in Hz */ + fin = icn->dsi->hs_rate / 4; /* in Hz */ /* Minimum value of P predivider for PLL input in 5..20 MHz */ p_min = clamp(DIV_ROUND_UP(fin, 20000000), 1U, 31U); @@ -515,6 +514,8 @@ static int chipone_dsi_attach(struct chipone *icn) dsi->format = MIPI_DSI_FMT_RGB888; dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET; + dsi->hs_rate = 500000000; + dsi->lp_rate = 16000000; ret = mipi_dsi_attach(dsi); if (ret < 0)
Fill in hs_rate and lp_rate to struct mipi_dsi_device for this bridge and adjust DSI input frequency calculations such that they expect the DSI host to configure HS clock according to hs_rate. This is an optimization for the DSI burst mode case. In case the DSI device supports DSI burst mode, it is recommended to operate the DSI interface at the highest possible HS clock frequency which the DSI device supports. This permits the DSI host to send as short as possible bursts of data on the DSI link and keep the DSI data lanes in LP mode otherwise, which reduces power consumption. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Robert Foss <robert.foss@linaro.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: dri-devel@lists.freedesktop.org --- drivers/gpu/drm/bridge/chipone-icn6211.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)