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SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(39860400002)(136003)(376002)(346002)(396003)(46966006)(40470700004)(36840700001)(36756003)(7696005)(478600001)(6666004)(86362001)(41300700001)(26005)(356005)(81166007)(2616005)(1076003)(47076005)(336012)(16526019)(186003)(426003)(83380400001)(82310400005)(40480700001)(70206006)(5660300002)(4326008)(8676002)(316002)(6916009)(70586007)(54906003)(36860700001)(82740400003)(44832011)(8936002)(2906002)(40460700003)(16060500005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Aug 2022 18:00:10.9491 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d6b4697c-eefd-4c26-1423-08da7bc3558c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4053 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anders Roxell , Thomas Zimmermann , Leo Li , dri-devel@lists.freedesktop.org, "Pan, Xinhui" , Rodrigo Siqueira , Roman Li , amd-gfx@lists.freedesktop.org, =?utf-8?q?Christian_K=C3=B6nig?= , David Airlie , Fangzhi Zuo , hersen wu , Hamza Mahfooz , Wayne Lin , Alex Deucher , Nicholas Kazlauskas , Sudip Mukherjee Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Need to protect DSC code with CONFIG_DRM_AMD_DC_DCN. Fixes the following build errors on arm64: ERROR: modpost: "dc_dsc_get_policy_for_timing" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "dc_dsc_compute_bandwidth_range" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! Fixes: 0087990a9f57 ("drm/amd/display: consider DSC pass-through during mode validation") Reported-by: Anders Roxell Signed-off-by: Hamza Mahfooz Tested-by: Sudip Mukherjee Tested-by: Anders Roxell Reviewed-by: Alex Deucher --- v2: Fix WERROR build failure by guarding unused variables --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index ef6c94cd852b..ce6929224a6e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1387,8 +1387,6 @@ bool pre_validate_dsc(struct drm_atomic_state *state, return (ret == 0); } -#endif - static unsigned int kbps_from_pbn(unsigned int pbn) { unsigned int kbps = pbn; @@ -1416,17 +1414,19 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream, return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16; } +#endif /* CONFIG_DRM_AMD_DC_DCN */ enum dc_status dm_dp_mst_is_port_support_mode( struct amdgpu_dm_connector *aconnector, struct dc_stream_state *stream) { + int bpp, pbn, branch_max_throughput_mps = 0; +#if defined(CONFIG_DRM_AMD_DC_DCN) struct dc_link_settings cur_link_settings; unsigned int end_to_end_bw_in_kbps = 0; unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0; unsigned int max_compressed_bw_in_kbps = 0; struct dc_dsc_bw_range bw_range = {0}; - int bpp, pbn, branch_max_throughput_mps = 0; /* * check if the mode could be supported if DSC pass-through is supported @@ -1461,13 +1461,16 @@ enum dc_status dm_dp_mst_is_port_support_mode( return DC_FAIL_BANDWIDTH_VALIDATE; } } else { +#endif /* check if mode could be supported within full_pbn */ bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3; pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false); if (pbn > aconnector->port->full_pbn) return DC_FAIL_BANDWIDTH_VALIDATE; +#if defined(CONFIG_DRM_AMD_DC_DCN) } +#endif /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */ switch (stream->timing.pixel_encoding) {