From patchwork Sat Oct 1 08:06:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 12996464 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12D03C433FE for ; Sat, 1 Oct 2022 08:10:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F07D210E531; Sat, 1 Oct 2022 08:10:34 +0000 (UTC) Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by gabe.freedesktop.org (Postfix) with ESMTPS id C909A10E531 for ; Sat, 1 Oct 2022 08:10:30 +0000 (UTC) Received: by mail-pf1-x42b.google.com with SMTP id i6so6141091pfb.2 for ; Sat, 01 Oct 2022 01:10:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=kNa+Zfrt6fq++pnj2gbp7R05J06qVtRoBZLGkH8PcDw=; b=rQNF8tS3D8hzncMnTgYSuGc+gLkkyeTDUFY65I2upJJTz0b+WESJ7QdmimtnMWH0rb KW66vBsWy1Qq3Bf/PPvbOmOlqWjNvZMamWOOI9GYA8y64cylcg7ritGD9WU88bCHtFpL hdghmA0BNMDSthG9kGVOFyhVKmiWyW1/dfxeo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=kNa+Zfrt6fq++pnj2gbp7R05J06qVtRoBZLGkH8PcDw=; b=BtTPBW6oX+X1ac5xo/4OkKu+veoBEz37bQlOT3TzyFv/lqPdMyf29f4j4uSlgKIb/d +Kw7FH7NDeIquc+nlddROHj8I72XusYEDB6dE/n9Qy6R6COGp8RQdPwOJIhkGGGzytK+ /RDoSwg23cP7h6sS0AhSYn/WNJqb4T+1fP2HlXJRMeEVn0qPdw4h2apYfP4n6U2fdv3n k8N3mWRxgBYnxj+KlBSId/EHn4rTS8tLyn3M0eS3DxUOpQtviAM9cl80rYfnMatYDGP3 hkNUo4VIq2dfQvSFtALPBvNeJLRpF1HEHFkPyqVrorIf9gBWYP/6V9qeDFOGrCZRPvxg iOkA== X-Gm-Message-State: ACrzQf2UncqiM9L9d3/Xrkeui9qZ+ZnlIk1K7s8RyGVqK1GP/TFJh4pw 9B0bX0G+zmOQxOIgDB+RGNZJ1g== X-Google-Smtp-Source: AMsMyM6c3fu8pImibJC5IG2/qhDWNilZ4L/Bcb8g67ranqSll74i2Xn5H+8BxaQu6z3I3bCVKDOp0w== X-Received: by 2002:a05:6a00:cd6:b0:546:d03:3dd7 with SMTP id b22-20020a056a000cd600b005460d033dd7mr12926362pfv.19.1664611830363; Sat, 01 Oct 2022 01:10:30 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c00a:a073:7254:4392:bc7c:c69]) by smtp.gmail.com with ESMTPSA id c194-20020a624ecb000000b005409c9d2d41sm3167041pfb.62.2022.10.01.01.10.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 01:10:29 -0700 (PDT) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Fancy Fang , Tim Harvey , Michael Nazzareno Trimarchi , Adam Ford , Neil Armstrong , Robert Foss , Laurent Pinchart , Tommaso Merciai , Marek Vasut Subject: [PATCH v6 10/10] drm: bridge: samsung-dsim: Add i.MX8MM support Date: Sat, 1 Oct 2022 13:36:50 +0530 Message-Id: <20221001080650.1007043-11-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221001080650.1007043-1-jagan@amarulasolutions.com> References: <20221001080650.1007043-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-samsung-soc@vger.kernel.org, Laurent Pinchart , Matteo Lisi , dri-devel@lists.freedesktop.org, NXP Linux Team , linux-amarula , linux-arm-kernel@lists.infradead.org, Jagan Teki Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Samsung MIPI DSIM master can also be found in i.MX8MM SoC. Add compatible and associated driver_data for it. v6: * none v3: * enable DSIM_QUIRK_FIXUP_SYNC_POL quirk v5: * [mszyprow] rebased and adjusted to the new driver initialization * drop quirk v4: * none v3: * enable DSIM_QUIRK_FIXUP_SYNC_POL quirk v2: * collect Laurent r-b v1: * none Reviewed-by: Laurent Pinchart Signed-off-by: Marek Szyprowski Signed-off-by: Jagan Teki --- drivers/gpu/drm/bridge/samsung-dsim.c | 45 +++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 49406a07d655..5f2c51428cdd 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -360,6 +360,24 @@ static const unsigned int exynos5433_reg_values[] = { [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), }; +static const unsigned int imx8mm_dsim_reg_values[] = { + [RESET_TYPE] = DSIM_SWRST, + [PLL_TIMER] = 500, + [STOP_STATE_CNT] = 0xf, + [PHYCTRL_ULPS_EXIT] = 0, + [PHYCTRL_VREG_LP] = 0, + [PHYCTRL_SLEW_UP] = 0, + [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), + [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), + [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), + [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26), + [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), + [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), + [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08), + [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), + [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), +}; + static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { .reg_ofs = exynos_reg_ofs, .plltmr_reg = 0x50, @@ -421,6 +439,23 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { .reg_values = exynos5422_reg_values, }; +static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { + .reg_ofs = exynos5433_reg_ofs, + .plltmr_reg = 0xa0, + .has_clklane_stop = 1, + .num_clks = 2, + .max_freq = 2100, + .wait_for_reset = 0, + .num_bits_resol = 12, + /** + * FIXME: + * Offset value used from downstream drivers/gpu/drm/bridge/sec-dsim.c + * remove this comment if it is true else update the logic. + */ + .pll_p_offset = 14, + .reg_values = imx8mm_dsim_reg_values, +}; + static const struct samsung_dsim_driver_data * samsung_dsim_types[SAMSUNG_DSIM_TYPE_COUNT] = { [SAMSUNG_DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data, @@ -428,6 +463,7 @@ samsung_dsim_types[SAMSUNG_DSIM_TYPE_COUNT] = { [SAMSUNG_DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data, [SAMSUNG_DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data, [SAMSUNG_DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data, + [SAMSUNG_DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data, }; static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h) @@ -1788,7 +1824,16 @@ const struct dev_pm_ops samsung_dsim_pm_ops = { }; EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops); +static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = { + .hw_type = SAMSUNG_DSIM_TYPE_IMX8MM, + .host_ops = &samsung_dsim_generic_host_ops, +}; + static const struct of_device_id samsung_dsim_of_match[] = { + { + .compatible = "fsl,imx8mm-mipi-dsim", + .data = &samsung_dsim_imx8mm_pdata, + }, { /* sentinel. */ } }; MODULE_DEVICE_TABLE(of, samsung_dsim_of_match);