| Message ID | 20221115133105.980877-7-robert.foss@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable Display for SM8350 | expand |
On 15/11/2022 14:30, Robert Foss wrote: > Add compatibles string, "qcom,sm8350-mdss", for the multimedia display > subsystem unit used on Qualcomm SM8350 platform. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > drivers/gpu/drm/msm/msm_mdss.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > index a2264fb517a1..39746b972cdd 100644 > --- a/drivers/gpu/drm/msm/msm_mdss.c > +++ b/drivers/gpu/drm/msm/msm_mdss.c > @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) > /* UBWC_2_0 */ > msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e); > break; > + case DPU_HW_VER_700: > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1); > + break; Shouldn't the second-last argument be 2 or 3 depending on DDR type? Konrad > case DPU_HW_VER_720: > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); > break; > @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = { > { .compatible = "qcom,sc8180x-mdss" }, > { .compatible = "qcom,sm8150-mdss" }, > { .compatible = "qcom,sm8250-mdss" }, > + { .compatible = "qcom,sm8350-mdss" }, > { .compatible = "qcom,sm8450-mdss" }, > {} > };
On Tue, 15 Nov 2022 at 14:42, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > > > On 15/11/2022 14:30, Robert Foss wrote: > > Add compatibles string, "qcom,sm8350-mdss", for the multimedia display > > subsystem unit used on Qualcomm SM8350 platform. > > > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > --- > > drivers/gpu/drm/msm/msm_mdss.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > > index a2264fb517a1..39746b972cdd 100644 > > --- a/drivers/gpu/drm/msm/msm_mdss.c > > +++ b/drivers/gpu/drm/msm/msm_mdss.c > > @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) > > /* UBWC_2_0 */ > > msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e); > > break; > > + case DPU_HW_VER_700: > > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1); > > + break; > Shouldn't the second-last argument be 2 or 3 depending on DDR type? Dmitry, can I get your input on this? I'm a little bit unsure of which dts properties some of these values are derived from. > > Konrad > > case DPU_HW_VER_720: > > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); > > break; > > @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = { > > { .compatible = "qcom,sc8180x-mdss" }, > > { .compatible = "qcom,sm8150-mdss" }, > > { .compatible = "qcom,sm8250-mdss" }, > > + { .compatible = "qcom,sm8350-mdss" }, > > { .compatible = "qcom,sm8450-mdss" }, > > {} > > };
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index a2264fb517a1..39746b972cdd 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) /* UBWC_2_0 */ msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e); break; + case DPU_HW_VER_700: + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1); + break; case DPU_HW_VER_720: msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); break; @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sc8180x-mdss" }, { .compatible = "qcom,sm8150-mdss" }, { .compatible = "qcom,sm8250-mdss" }, + { .compatible = "qcom,sm8350-mdss" }, { .compatible = "qcom,sm8450-mdss" }, {} };
Add compatibles string, "qcom,sm8350-mdss", for the multimedia display subsystem unit used on Qualcomm SM8350 platform. Signed-off-by: Robert Foss <robert.foss@linaro.org> --- drivers/gpu/drm/msm/msm_mdss.c | 4 ++++ 1 file changed, 4 insertions(+)