| Message ID | 20221123065946.40415-6-tomi.valkeinen+renesas@ideasonboard.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Renesas V4H DSI & DP output support | expand |
Hi Tomi, On Wed, Nov 23, 2022 at 8:00 AM Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> wrote: > Add DT nodes needed for the mini DP connector. The DP is driven by > sn65dsi86, which in turn gets the pixel data from the SoC via DSI. > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> > Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Thanks for your patch! Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.3, with the mini-dp-con node moved up. > --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi > @@ -97,6 +97,15 @@ memory@600000000 { > reg = <0x6 0x00000000 0x1 0x00000000>; > }; > > + reg_1p2v: regulator-1p2v { > + compatible = "regulator-fixed"; > + regulator-name = "fixed-1.2V"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > reg_1p8v: regulator-1p8v { > compatible = "regulator-fixed"; > regulator-name = "fixed-1.8V"; > @@ -114,6 +123,24 @@ reg_3p3v: regulator-3p3v { > regulator-boot-on; > regulator-always-on; > }; > + > + mini-dp-con { > + compatible = "dp-connector"; > + label = "CN5"; > + type = "mini"; > + > + port { > + mini_dp_con_in: endpoint { > + remote-endpoint = <&sn65dsi86_out>; > + }; > + }; > + }; Moving up while applying to preserve sort order... > + > + sn65dsi86_refclk: clk-x6 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <38400000>; > + }; > }; > > &avb0 { > @@ -172,6 +216,51 @@ eeprom@50 { > }; > }; > > +&i2c1 { > + pinctrl-0 = <&i2c1_pins>; > + pinctrl-names = "default"; > + > + status = "okay"; > + clock-frequency = <400000>; > + > + bridge@2c { Ideally, this needs pinctrl for the intc_ex irq0 pin. Unfortunately[1] is still in limbo as the naming of the alternate pins is inconsistent. > + compatible = "ti,sn65dsi86"; > + reg = <0x2c>; > + > + clocks = <&sn65dsi86_refclk>; > + clock-names = "refclk"; > + > + interrupt-parent = <&intc_ex>; > + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; > + > + enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; > + > + vccio-supply = <®_1p8v>; > + vpll-supply = <®_1p8v>; > + vcca-supply = <®_1p2v>; > + vcc-supply = <®_1p2v>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + sn65dsi86_in: endpoint { > + remote-endpoint = <&dsi0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + sn65dsi86_out: endpoint { > + remote-endpoint = <&mini_dp_con_in>; > + }; > + }; > + }; > + }; > +}; > + > &mmc0 { > pinctrl-0 = <&mmc_pins>; > pinctrl-1 = <&mmc_pins>; [1] "[PATCH/RFC] pinctrl: renesas: r8a779g0: Add INTC-EX pins, groups, and function" https://lore.kernel.org/all/28fe05d41bea5a03ea6c8434f5a4fb6c80b48867.1664368425.git.geert+renesas@glider.be Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index c10740aee9f6..8aab859aac7a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -97,6 +97,15 @@ memory@600000000 { reg = <0x6 0x00000000 0x1 0x00000000>; }; + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -114,6 +123,24 @@ reg_3p3v: regulator-3p3v { regulator-boot-on; regulator-always-on; }; + + mini-dp-con { + compatible = "dp-connector"; + label = "CN5"; + type = "mini"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + + sn65dsi86_refclk: clk-x6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; }; &avb0 { @@ -134,6 +161,23 @@ phy0: ethernet-phy@0 { }; }; +&dsi0 { + status = "okay"; + + ports { + port@1 { + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -172,6 +216,51 @@ eeprom@50 { }; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; +}; + &mmc0 { pinctrl-0 = <&mmc_pins>; pinctrl-1 = <&mmc_pins>; @@ -221,6 +310,11 @@ i2c0_pins: i2c0 { function = "i2c0"; }; + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + keys_pins: keys { pins = "GP_5_0", "GP_5_1", "GP_5_2"; bias-pull-up;