[v3,08/11] drm/amd: Request GFX9 microcode during IP discovery

Message ID	20221230052119.15096-9-mario.limonciello@amd.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <dri-devel-bounces@lists.freedesktop.org> Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Mario Limonciello <mario.limonciello@amd.com> To: Alex Deucher <alexander.deucher@amd.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH v3 08/11] drm/amd: Request GFX9 microcode during IP discovery Date: Thu, 29 Dec 2022 23:21:12 -0600 Message-ID: <20221230052119.15096-9-mario.limonciello@amd.com> In-Reply-To: <20221230052119.15096-1-mario.limonciello@amd.com> References: <20221230052119.15096-1-mario.limonciello@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: list Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com>, Javier Martinez Canillas <javierm@redhat.com>, dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez <csoriano@redhat.com>, christian.koenig@amd.com, Mario Limonciello <mario.limonciello@amd.com> Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org>
Series	Recover from failure to probe GPU \| expand [v3,00/11] Recover from failure to probe GPU [v3,01/11] drm/amd: Delay removal of the firmware framebuffer [v3,02/11] drm/amd: Add a legacy mapping to "amdgpu_ucode_ip_version_decode" [v3,03/11] drm/amd: Convert SMUv11 microcode init to use `amdgpu_ucode_ip_version_decode` [v3,04/11] drm/amd: Convert SMUv13 to use `amdgpu_ucode_ip_version_decode` [v3,05/11] drm/amd: Request SDMA microcode during IP discovery [v3,06/11] drm/amd: Request VCN microcode during IP discovery [v3,07/11] drm/amd: Request MES microcode during IP discovery [v3,08/11] drm/amd: Request GFX9 microcode during IP discovery [v3,09/11] drm/amd: Request GFX10 microcode during IP discovery [v3,10/11] drm/amd: Request GFX11 microcode during IP discovery [v3,11/11] drm/amd: Request PSP microcode during IP discovery

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index edaeec35c39f..0ff1b3872441 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -158,6 +158,68 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); + +/* gfx9 */ +MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); +MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); +MODULE_FIRMWARE("amdgpu/vega10_me.bin"); +MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); +MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); +MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); +MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); +MODULE_FIRMWARE("amdgpu/vega12_me.bin"); +MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); +MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); +MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); +MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); +MODULE_FIRMWARE("amdgpu/vega20_me.bin"); +MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); +MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); +MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/raven_ce.bin"); +MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); +MODULE_FIRMWARE("amdgpu/raven_me.bin"); +MODULE_FIRMWARE("amdgpu/raven_mec.bin"); +MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); +MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); +MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); +MODULE_FIRMWARE("amdgpu/picasso_me.bin"); +MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); +MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); +MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); +MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); + +MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); +MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); +MODULE_FIRMWARE("amdgpu/raven2_me.bin"); +MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); +MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); +MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); +MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); +MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); +MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); +MODULE_FIRMWARE("amdgpu/renoir_me.bin"); +MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); +MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); + static const char *hw_id_names[HW_ID_MAX] = { [MP1_HWID] = "MP1", [MP2_HWID] = "MP2", @@ -1845,8 +1907,90 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) return 0; } +static int amdgpu_discovery_load_gfx9(struct amdgpu_device *adev, char *ucode_prefix) +{ + uint32_t smu_version; + char fw_name[40]; + int r; + + switch (adev->ip_versions[GC_HWIP][0]) { + /* No CPG in Arcturus */ + case IP_VERSION(9, 4, 1): + case IP_VERSION(9, 4, 2): + break; + default: + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); + r = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + if (r) + return r; + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); + r = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + if (r) + return r; + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", ucode_prefix); + r = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + if (r) + return r; + } + + if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", ucode_prefix); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); + r = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + if (r) + return r; + + /* + * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin + * instead of picasso_rlc.bin. + * Judgment method: + * PCO AM4: revision >= 0xC8 && revision <= 0xCF + * or revision >= 0xD8 && revision <= 0xDF + * otherwise is PCO FP5 + */ + if (!strcmp(ucode_prefix, "picasso") && + (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || + ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", ucode_prefix); + else if (!strcmp(ucode_prefix, "raven") && + (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && + (smu_version >= 0x41e2b)) + /* SMC is loaded by SBIOS on APU & can get the SMU version directly. */ + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", ucode_prefix); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); + r = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); + if (r) + return r; + + /* mec2 fw bin support */ + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) { + + if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", ucode_prefix); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", ucode_prefix); + + r = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + if (r) + return r; + } + + return 0; +} + static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) { + char ucode_prefix[30]; + int r; + + amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); + switch (adev->ip_versions[GC_HWIP][0]) { case IP_VERSION(9, 0, 1): case IP_VERSION(9, 1, 0): @@ -1856,6 +2000,9 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(9, 4, 0): case IP_VERSION(9, 4, 1): case IP_VERSION(9, 4, 2): + r = amdgpu_discovery_load_gfx9(adev, ucode_prefix); + if (r) + return r; amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); break; case IP_VERSION(10, 1, 10): diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index f202b45c413c..9288a3bcb3c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -65,72 +65,6 @@ #define mmGCEA_PROBE_MAP 0x070c #define mmGCEA_PROBE_MAP_BASE_IDX 0 -MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); -MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); -MODULE_FIRMWARE("amdgpu/vega10_me.bin"); -MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); -MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); -MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); -MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); -MODULE_FIRMWARE("amdgpu/vega12_me.bin"); -MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); -MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); -MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); -MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); -MODULE_FIRMWARE("amdgpu/vega20_me.bin"); -MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); -MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); -MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/raven_ce.bin"); -MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); -MODULE_FIRMWARE("amdgpu/raven_me.bin"); -MODULE_FIRMWARE("amdgpu/raven_mec.bin"); -MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); -MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); -MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); -MODULE_FIRMWARE("amdgpu/picasso_me.bin"); -MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); -MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); -MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); -MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); - -MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); -MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); -MODULE_FIRMWARE("amdgpu/raven2_me.bin"); -MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); -MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); -MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); -MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); -MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); -MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); -MODULE_FIRMWARE("amdgpu/renoir_me.bin"); -MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); -MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin"); - #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 @@ -1250,34 +1184,20 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) } } -static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, - const char *chip_name) +static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev) { - char fw_name[30]; int err; - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.pfp_fw); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.me_fw); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); - err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.ce_fw); if (err) goto out; @@ -1286,8 +1206,7 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, out: if (err) { dev_err(adev->dev, - "gfx9: Failed to init firmware \"%s\"\n", - fw_name); + "gfx9: Failed to init firmware\n"); release_firmware(adev->gfx.pfp_fw); adev->gfx.pfp_fw = NULL; release_firmware(adev->gfx.me_fw); @@ -1298,39 +1217,13 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, return err; } -static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, - const char *chip_name) +static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev) { - char fw_name[30]; int err; const struct rlc_firmware_header_v2_0 *rlc_hdr; uint16_t version_major; uint16_t version_minor; - uint32_t smu_version; - /* - * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin - * instead of picasso_rlc.bin. - * Judgment method: - * PCO AM4: revision >= 0xC8 && revision <= 0xCF - * or revision >= 0xD8 && revision <= 0xDF - * otherwise is PCO FP5 - */ - if (!strcmp(chip_name, "picasso") && - (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || - ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name); - else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && - (smu_version >= 0x41e2b)) - /** - *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly. - */ - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); - err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.rlc_fw); if (err) goto out; @@ -1342,8 +1235,7 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, out: if (err) { dev_err(adev->dev, - "gfx9: Failed to init firmware \"%s\"\n", - fw_name); + "gfx9: Failed to init firmware\n"); release_firmware(adev->gfx.rlc_fw); adev->gfx.rlc_fw = NULL; } @@ -1360,20 +1252,10 @@ static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev) return true; } -static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, - const char *chip_name) +static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev) { - char fw_name[30]; int err; - if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); - - err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.mec_fw); if (err) goto out; @@ -1381,22 +1263,11 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { - if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); - - err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); - if (!err) { - err = amdgpu_ucode_validate(adev->gfx.mec2_fw); - if (err) - goto out; - amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); - amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); - } else { - err = 0; - adev->gfx.mec2_fw = NULL; - } + err = amdgpu_ucode_validate(adev->gfx.mec2_fw); + if (err) + goto out; + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); } else { adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; @@ -1407,8 +1278,7 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, gfx_v9_0_check_fw_write_wait(adev); if (err) { dev_err(adev->dev, - "gfx9: Failed to init firmware \"%s\"\n", - fw_name); + "gfx9: Failed to init firmware\n"); release_firmware(adev->gfx.mec_fw); adev->gfx.mec_fw = NULL; release_firmware(adev->gfx.mec2_fw); @@ -1419,58 +1289,22 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) { - const char *chip_name; int r; DRM_DEBUG("\n"); - switch (adev->ip_versions[GC_HWIP][0]) { - case IP_VERSION(9, 0, 1): - chip_name = "vega10"; - break; - case IP_VERSION(9, 2, 1): - chip_name = "vega12"; - break; - case IP_VERSION(9, 4, 0): - chip_name = "vega20"; - break; - case IP_VERSION(9, 2, 2): - case IP_VERSION(9, 1, 0): - if (adev->apu_flags & AMD_APU_IS_RAVEN2) - chip_name = "raven2"; - else if (adev->apu_flags & AMD_APU_IS_PICASSO) - chip_name = "picasso"; - else - chip_name = "raven"; - break; - case IP_VERSION(9, 4, 1): - chip_name = "arcturus"; - break; - case IP_VERSION(9, 3, 0): - if (adev->apu_flags & AMD_APU_IS_RENOIR) - chip_name = "renoir"; - else - chip_name = "green_sardine"; - break; - case IP_VERSION(9, 4, 2): - chip_name = "aldebaran"; - break; - default: - BUG(); - } - /* No CPG in Arcturus */ if (adev->gfx.num_gfx_rings) { - r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name); + r = gfx_v9_0_init_cp_gfx_microcode(adev); if (r) return r; } - r = gfx_v9_0_init_rlc_microcode(adev, chip_name); + r = gfx_v9_0_init_rlc_microcode(adev); if (r) return r; - r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name); + r = gfx_v9_0_init_cp_compute_microcode(adev); if (r) return r;

[v3,08/11] drm/amd: Request GFX9 microcode during IP discovery

Commit Message

Patch