From patchwork Mon Jan 9 09:26:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13093193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75D96C54EBD for ; Mon, 9 Jan 2023 09:26:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C4A2910E390; Mon, 9 Jan 2023 09:26:55 +0000 (UTC) Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1E61610E38F for ; Mon, 9 Jan 2023 09:26:44 +0000 (UTC) Received: by mail-wm1-x32c.google.com with SMTP id m26-20020a05600c3b1a00b003d9811fcaafso6100278wms.5 for ; Mon, 09 Jan 2023 01:26:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=E+gc0w5hWfVZt2wiZtuzeDBan9gl3xA+7WK6wQRAV74=; b=vKR0QOYI/rOQ+WlWBIrflT2ln+b39zy8uB716rTZAbLdI9vQG8ISOyBwI3KahNcoBa AX+wlowVJ/Ruw/tZMKaG8CejZQCkg+5v6vG0+mTuGS/VXS3dvmF0I/hrufdlHW7dDSvo OYl+9UN/tHO+tsaZJIzeLLnpH0Ak1haslInzwXEZgZNp1jYiXB7V955R2zuCAodHBKcX YhDNfTjocbNglLQFeTPqTHosBBtJqEl/XpR3td4ezNBY2TWa/KfYEXVb8SzyCLU5x3BB DQ+AltUqx9uXGM8CweD32P8kv1KaSpszHowRRbFr9JsobpZx1i96gb/YeHAWOM8kBoAG zOuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E+gc0w5hWfVZt2wiZtuzeDBan9gl3xA+7WK6wQRAV74=; b=z2rpUHELcYjijwxtKAuPHvuxTStXjyxWpFzxwfknHwaFXJJ2WdlJmpQyA2l1LFu/pG bkkZIsWsh4lDyOJdiyx1gy3M1jOzF+Zft4B/nTzB6o1gMrJ0v0t+ujbRp1pK7dVFzC1V AUeh4AKmysYic6IMzF8SOdMwft6BMUp+CRPVPlaDDEdE6rGy/I8qHRsPnDZACRI57Jqo oTuNfZTGQZsFSxbJdnxbCeXDigp0tPnvTdHlTciuz1GRBc1Moydrp9pC2HB5JeouP9FQ i6dZgh52pj0svrOBt9uaNJJ8NYivA8tItybYPOlPq04NIQJg2Qml/GMhW0M0h1bqS5N3 El5g== X-Gm-Message-State: AFqh2kq5VpLTtnqC5mGpGo1tJmqOsP/6PxyuzUQ/1RlJvyZJ5mO2Z0YH zD2nWN/W4f1fPYAuLrdWoOpprw== X-Google-Smtp-Source: AMrXdXuAO8AszQ04C4sIU8mdVvqVfTBv/kxLC3UPIki9fIDrZJL5BKOVJdSE4Kk3MNwKx2CiRByeiA== X-Received: by 2002:a05:600c:1e09:b0:3cf:b73f:bf8f with SMTP id ay9-20020a05600c1e0900b003cfb73fbf8fmr45111226wmb.7.1673256402579; Mon, 09 Jan 2023 01:26:42 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id s23-20020a1cf217000000b003d1e3b1624dsm15195758wmc.2.2023.01.09.01.26.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 01:26:42 -0800 (PST) From: Neil Armstrong Date: Mon, 09 Jan 2023 10:26:34 +0100 Subject: [PATCH v2 2/7] dt-bindings: display/msm: document DPU on SM8550 MIME-Version: 1.0 Message-Id: <20230103-topic-sm8550-upstream-mdss-dsi-v2-2-87f1c16d7635@linaro.org> References: <20230103-topic-sm8550-upstream-mdss-dsi-v2-0-87f1c16d7635@linaro.org> In-Reply-To: <20230103-topic-sm8550-upstream-mdss-dsi-v2-0-87f1c16d7635@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Jonathan Marek X-Mailer: b4 0.11.1 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Document the DPU hardware found on the Qualcomm SM8550 platform. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski --- .../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 +++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml new file mode 100644 index 000000000000..c3d5a98fe3c0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Display DPU + +maintainers: + - Neil Armstrong + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8550-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display AHB + - description: Display hf axi + - description: Display MDSS ahb + - description: Display lut + - description: Display core + - description: Display vsync + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-controller@ae01000 { + compatible = "qcom,sm8550-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8550_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +...