| Message ID | 20230123104742.227460-5-tomi.valkeinen+renesas@ideasonboard.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3,1/7] drm: rcar-du: dsi: add 'select RESET_CONTROLLER' | expand |
Hi Geert, On Mon, Jan 23, 2023 at 03:28:08PM +0100, Geert Uytterhoeven wrote: > On Mon, Jan 23, 2023 at 11:48 AM Tomi Valkeinen wrote: > > From: Koji Matsuoka <koji.matsuoka.xm@renesas.com> > > > > According to hardware manual, LVDCR0 register must be cleared bit by bit > > when disabling LVDS. > > > > Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> > > Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> > > [tomi.valkeinen: simplified the code a bit] > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > Thanks for your patch! > > > @@ -544,6 +549,27 @@ static void rcar_lvds_atomic_disable(struct drm_bridge *bridge, > > struct drm_bridge_state *old_bridge_state) > > { > > struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); > > + u32 lvdcr0; > > + > > + lvdcr0 = rcar_lvds_read(lvds, LVDCR0); > > + > > + lvdcr0 &= ~LVDCR0_LVRES; > > + rcar_lvds_write(lvds, LVDCR0, lvdcr0); > > + > > + if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) { > > + lvdcr0 &= ~LVDCR0_LVEN; > > + rcar_lvds_write(lvds, LVDCR0, lvdcr0); > > + } > > + > > + if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) { > > + lvdcr0 &= ~LVDCR0_PWD; > > + rcar_lvds_write(lvds, LVDCR0, lvdcr0); > > + } > > + > > + if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) { > > + lvdcr0 &= ~LVDCR0_PLLON; > > + rcar_lvds_write(lvds, LVDCR0, lvdcr0); > > + } > > Please add a comment explaining why there are multiple register writes, > to avoid an over-zealous janitor "optimizing" the code later. I'll add this comment at the top of the function: /* * Clear the LVDCR0 bits in the order specified by the hardware * documentation, ending with a write of 0 to the full register to * clear all remaining bits. */ > > > > rcar_lvds_write(lvds, LVDCR0, 0); > > rcar_lvds_write(lvds, LVDCR1, 0);
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c index a11201e4d31b..8cd86a3d65a5 100644 --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c @@ -83,6 +83,11 @@ struct rcar_lvds { #define bridge_to_rcar_lvds(b) \ container_of(b, struct rcar_lvds, bridge) +static u32 rcar_lvds_read(struct rcar_lvds *lvds, u32 reg) +{ + return ioread32(lvds->mmio + reg); +} + static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data) { iowrite32(data, lvds->mmio + reg); @@ -544,6 +549,27 @@ static void rcar_lvds_atomic_disable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state) { struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); + u32 lvdcr0; + + lvdcr0 = rcar_lvds_read(lvds, LVDCR0); + + lvdcr0 &= ~LVDCR0_LVRES; + rcar_lvds_write(lvds, LVDCR0, lvdcr0); + + if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) { + lvdcr0 &= ~LVDCR0_LVEN; + rcar_lvds_write(lvds, LVDCR0, lvdcr0); + } + + if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) { + lvdcr0 &= ~LVDCR0_PWD; + rcar_lvds_write(lvds, LVDCR0, lvdcr0); + } + + if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) { + lvdcr0 &= ~LVDCR0_PLLON; + rcar_lvds_write(lvds, LVDCR0, lvdcr0); + } rcar_lvds_write(lvds, LVDCR0, 0); rcar_lvds_write(lvds, LVDCR1, 0);