Message ID | 20230127145558.446123-1-maxime@cerno.tech (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | drm/vc4: crtc: Increase setup cost in core clock calculation to handle extreme reduced blanking | expand |
On Fri, 27 Jan 2023 15:55:58 +0100, Maxime Ripard wrote: > The formula that determines the core clock requirement based on pixel > clock and blanking has been determined experimentally to minimise the > clock while supporting all modes we've seen. > > A new reduced blanking mode (4kp60 at 533MHz rather than the standard > 594MHz) has been seen that doesn't produce a high enough clock and > results in "flip_done timed out" error. > > [...] Applied to drm/drm-misc (drm-misc-fixes). Thanks! Maxime
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index cdc0559221f0..bef9d45ef1df 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -722,7 +722,7 @@ int vc4_crtc_atomic_check(struct drm_crtc *crtc, struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) { - vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 1000, + vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 8000, mode->clock * 9 / 10) * 1000; } else { vc4_state->hvs_load = mode->clock * 1000;