| Message ID | 20230201222831.608281-2-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/4] drm/i915/pvc: Annotate two more workaround/tuning registers as MCR | expand |
On Wed, Feb 01, 2023 at 02:28:29PM -0800, Matt Roper wrote: > The UNSLICE_UNIT_LEVEL_CLKGATE register programmed by this workaround > has 'BUS' style reset, indicating that it does not lose its value on > engine resets. Furthermore, this register is part of the GT forcewake > domain rather than the RENDER domain, so it should not be impacted by > RCS engine resets. As such, we should implement this on the GT > workaround list rather than an engine list. > > Bspec: 19219 > Fixes: 3551ff928744 ("drm/i915/gen11: Moving WAs to rcs_engine_wa_init()") > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index f45ca3d4a07c..7e93ba6b3208 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1405,6 +1405,13 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > GAMT_CHKN_BIT_REG, > GAMT_CHKN_DISABLE_L3_COH_PIPE); > > + /* > + * Wa_1408615072:icl,ehl (vsunit) > + * Wa_1407596294:icl,ehl (hsunit) > + */ > + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, > + VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); > + > /* Wa_1407352427:icl,ehl */ > wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, > PSDUNIT_CLKGATE_DIS); > @@ -2536,13 +2543,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, > GEN11_ENABLE_32_PLANE_MODE); > > - /* > - * Wa_1408615072:icl,ehl (vsunit) > - * Wa_1407596294:icl,ehl (hsunit) > - */ > - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, > - VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); > - > /* > * Wa_1408767742:icl[a2..forever],ehl[all] > * Wa_1605460711:icl[a0..c0] > -- > 2.39.1 >
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index f45ca3d4a07c..7e93ba6b3208 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1405,6 +1405,13 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) GAMT_CHKN_BIT_REG, GAMT_CHKN_DISABLE_L3_COH_PIPE); + /* + * Wa_1408615072:icl,ehl (vsunit) + * Wa_1407596294:icl,ehl (hsunit) + */ + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, + VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); + /* Wa_1407352427:icl,ehl */ wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, PSDUNIT_CLKGATE_DIS); @@ -2536,13 +2543,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, GEN11_ENABLE_32_PLANE_MODE); - /* - * Wa_1408615072:icl,ehl (vsunit) - * Wa_1407596294:icl,ehl (hsunit) - */ - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, - VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); - /* * Wa_1408767742:icl[a2..forever],ehl[all] * Wa_1605460711:icl[a0..c0]
The UNSLICE_UNIT_LEVEL_CLKGATE register programmed by this workaround has 'BUS' style reset, indicating that it does not lose its value on engine resets. Furthermore, this register is part of the GT forcewake domain rather than the RENDER domain, so it should not be impacted by RCS engine resets. As such, we should implement this on the GT workaround list rather than an engine list. Bspec: 19219 Fixes: 3551ff928744 ("drm/i915/gen11: Moving WAs to rcs_engine_wa_init()") Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)