From patchwork Tue Feb 14 17:31:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13140690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38B59C61DA4 for ; Tue, 14 Feb 2023 17:32:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 877AA10E22E; Tue, 14 Feb 2023 17:32:01 +0000 (UTC) Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by gabe.freedesktop.org (Postfix) with ESMTPS id 96E1910E22E for ; Tue, 14 Feb 2023 17:31:59 +0000 (UTC) Received: by mail-ed1-x52d.google.com with SMTP id dz21so6456289edb.13 for ; Tue, 14 Feb 2023 09:31:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NtwSHEkotufMeTG5DbRKqbem2u4ITIQrgm1+z8QXytg=; b=dudwPRcx9NWJxqh2WdbBeETUJCwf5veKvmG4eZVchC9vAVm37Ifs7wbC5kEH1f5aWJ 8Ai2vSiSqC3wlxDmJB9k155jsoaUX/c3jfT+LnFoegMR73rY05zHBC5/+z8kv+NJWJ+C G36TY/dqZ5ze55PSyvYQBPyaPqZxTEcd4degUgHLhl4oFGZ2W76x47HN0GTCga+GJdPT 2ZFFA96BDrvB2VCI2Qt55oA2DXBBBJxn2NCedmKFpSwY3zV2V3rVaAjphoZkDaWUuoar k/ajkp1xaU8sjjmS6n5CK6BdWpEFJSs0+QL/j9qPKAwaW1kaYyNcGCcMkmofvyw/rIvW yJ8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NtwSHEkotufMeTG5DbRKqbem2u4ITIQrgm1+z8QXytg=; b=lcECFx42TSAteFsokzOIBYZbk3HefGIhyTXNKi+9K2ecKSKdsalzoba0/8JEjafpqF rg8ZcxJlsOihQS6CfWBpGu73tIzmjjMscJwLezkmmGI8Pve8aqEf/cyvxP3UnFPeaOVs oxAaD3b/2tHDdxTmUTn8Gm9LIuGifaFSjxIx7X8X8hOmpDqSyLvCVRjMGlYi77EPielv I56KoWomG5CCCLOezy+Yknm/bhjYMsV24JdOqsLhqegH8Cgi/+wjiWXgyQhR/xmwiLur nB2TXE33XbR8XY4BSVow1klYVUh/WTEyZHIcgSRLkHcqScLmZQXqIGW0itn7yY3fj1/K UFcQ== X-Gm-Message-State: AO0yUKX4LeD3zk0xM12nSHjJHuTk+cU6umnZLMG/VBIV98Lxza+YdINx LFnxzuvh7krZBw7JJaYJ5kD7iQ== X-Google-Smtp-Source: AK7set/+N7w1aYgI3Wl60vD5XAtpbT/GpSI4RIgCIKOAmMKYpmjMPrAUH20T6uuXF7ivxMar4Q7nNA== X-Received: by 2002:a50:d694:0:b0:4ac:b858:37b1 with SMTP id r20-20020a50d694000000b004acb85837b1mr3740065edi.7.1676395917889; Tue, 14 Feb 2023 09:31:57 -0800 (PST) Received: from localhost.localdomain (abxh117.neoplus.adsl.tpnet.pl. [83.9.1.117]) by smtp.gmail.com with ESMTPSA id w8-20020a50c448000000b0049668426aa6sm8325787edf.24.2023.02.14.09.31.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 09:31:57 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Subject: [PATCH v2 02/14] drm/msm/a6xx: Extend UBWC config Date: Tue, 14 Feb 2023 18:31:33 +0100 Message-Id: <20230214173145.2482651-3-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214173145.2482651-1-konrad.dybcio@linaro.org> References: <20230214173145.2482651-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: freedreno@lists.freedesktop.org, Akhil P Oommen , Abhinav Kumar , dri-devel@lists.freedesktop.org, Douglas Anderson , Konrad Dybcio , Dmitry Baryshkov , marijn.suijten@somainline.org, Sean Paul , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Port setting min_access_length, ubwc_mode and upper_bit from downstream. Values were validated using downstream device trees for SM8[123]50 and left default (as per downstream) elsewhere. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 29 +++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c5f5d0bb3fdc..8855d798bbb3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -786,17 +786,25 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - u32 lower_bit = 2; + u32 lower_bit = 1; + u32 upper_bit = 0; u32 amsbc = 0; u32 rgb565_predicator = 0; u32 uavflagprd_inv = 0; + u32 min_acc_len = 0; + u32 ubwc_mode = 0; /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) return; - if (adreno_is_a640_family(adreno_gpu)) + if (adreno_is_a630(adreno_gpu)) + lower_bit = 2; + + if (adreno_is_a640_family(adreno_gpu)) { amsbc = 1; + lower_bit = 2; + } if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ @@ -807,18 +815,23 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) } if (adreno_is_7c3(adreno_gpu)) { - lower_bit = 1; amsbc = 1; rgb565_predicator = 1; uavflagprd_inv = 2; } gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, - rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); - gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, - uavflagprd_inv << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); + rgb565_predicator << 11 | upper_bit << 10 | amsbc << 4 | + min_acc_len << 3 | lower_bit << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, upper_bit << 4 | + min_acc_len << 3 | lower_bit << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, upper_bit << 10 | + uavflagprd_inv << 4 | min_acc_len << 3 | + lower_bit << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | lower_bit << 21); } static int a6xx_cp_init(struct msm_gpu *gpu)