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[83.9.1.117]) by smtp.gmail.com with ESMTPSA id w8-20020a50c448000000b0049668426aa6sm8325787edf.24.2023.02.14.09.32.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 09:32:10 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Subject: [PATCH v2 06/14] drm/msm/gpu: Use dev_pm_opp_set_rate for non-GMU GPUs Date: Tue, 14 Feb 2023 18:31:37 +0100 Message-Id: <20230214173145.2482651-7-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214173145.2482651-1-konrad.dybcio@linaro.org> References: <20230214173145.2482651-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: freedreno@lists.freedesktop.org, Dan Carpenter , Emma Anholt , Akhil P Oommen , Abhinav Kumar , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov , marijn.suijten@somainline.org, Sean Paul Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Currently we only utilize the OPP table connected to the GPU for getting (available) frequencies. We do however need to scale the voltage rail(s) accordingly to ensure that we aren't trying to run the GPU at 1GHz with a VDD_LOW vote, as that would result in an otherwise inexplainable hang. Tell the OPP framework that we want to scale the "core" clock and swap out the clk_set_rate to a dev_pm_opp_set_rate in msm_devfreq_target() to enable usage of required-opps and by extension proper voltage level/corner scaling. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 ++++ drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index ce6b76c45b6f..15e405e4f977 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1047,6 +1047,10 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, const char *gpu_name; u32 speedbin; + /* This can only be done here, or devm_pm_opp_set_supported_hw will WARN_ON() */ + if (!IS_ERR(devm_clk_get(dev, "core"))) + devm_pm_opp_set_clkname(dev, "core"); + adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); adreno_gpu->gmem = adreno_gpu->info->gmem; diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c index e27dbf12b5e8..ea70c1c32d94 100644 --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c @@ -48,7 +48,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq, gpu->funcs->gpu_set_freq(gpu, opp, df->suspended); mutex_unlock(&df->lock); } else { - clk_set_rate(gpu->core_clk, *freq); + dev_pm_opp_set_rate(dev, *freq); } dev_pm_opp_put(opp);