From patchwork Mon Feb 27 11:39:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13153339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56937C7EE2D for ; Mon, 27 Feb 2023 11:41:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8B12310E3EA; Mon, 27 Feb 2023 11:41:32 +0000 (UTC) Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by gabe.freedesktop.org (Postfix) with ESMTPS id F1D1910E3EA for ; Mon, 27 Feb 2023 11:41:29 +0000 (UTC) Received: by mail-pj1-x102e.google.com with SMTP id h17-20020a17090aea9100b0023739b10792so5916879pjz.1 for ; Mon, 27 Feb 2023 03:41:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UvZwD67eFCMqJHDIBTDsxpjzh+agmIoxVCrI5gJq49Y=; b=GBF68+E7Cmzo3rsD969zbGmpoC4TvJaKmaG5c8b5XM79vWTWZnmRjpGtTnZA1k4nem 4JMGmlR2nadxNPlnY8+gfAoIhvR3/0jP4by4jkKqGCypf5wXzLbPLQHWsCaWR6ei0th/ m7Hwa5LnVBOLNZmE+ZuM6lYP2nFcXhWldZLec= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UvZwD67eFCMqJHDIBTDsxpjzh+agmIoxVCrI5gJq49Y=; b=TjHiTqXCw6oZB9OqOeOzhi60K+6it0nMT60FUf3jNTVaQUvzSE1Hsp8NW5qoZrUoIr MmxqvMfsC7t+09q8Z/txtZzm60qlMeYL24mt9Ah1vRku75LQIeWg+u9lxVER3WU7PBTN tJW7E0tY4aSnX50SzybGZ35rqWg50C0JuBcQ3FB4rzLotLPJ2LwYMNr9UPEMlt/dOMl4 MsC67odI5v1UCUnbA426Zn5A754cg36sqKpwTOVlTmEVt7XKJ2hkFW221q42WlU1PUcx AJm7rgSUcjxXtCrMe6MofU8rjwWpM71evYp/NmbOgoCk2jA6Kqf89adg8x9/Q0KyBXrs /xiw== X-Gm-Message-State: AO0yUKUZypy1fEKkn1KET74oV+0H9EjXhqOklT5hbwNpL8TBhNJuKU+Y 80LzpSp5DjI5dlUUPMAI7Dm2lw== X-Google-Smtp-Source: AK7set+lH8IlVJjjGUuzCQ1acMJmqOz2Irk9COU0b1CgAgrvL2pGYSNQ1wh/gSXRBDiC7XgZXZJ90g== X-Received: by 2002:a17:902:ec81:b0:19a:a80e:a6d5 with SMTP id x1-20020a170902ec8100b0019aa80ea6d5mr29294753plg.23.1677498089563; Mon, 27 Feb 2023 03:41:29 -0800 (PST) Received: from localhost.localdomain ([94.140.8.120]) by smtp.gmail.com with ESMTPSA id k10-20020a170902ba8a00b0019c919bccf8sm4395277pls.86.2023.02.27.03.41.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 03:41:29 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Laurent Pinchart , Marek Vasut Subject: [PATCH v13 16/18] drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support Date: Mon, 27 Feb 2023 17:09:23 +0530 Message-Id: <20230227113925.875425-17-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230227113925.875425-1-jagan@amarulasolutions.com> References: <20230227113925.875425-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-samsung-soc@vger.kernel.org, Laurent Pinchart , Matteo Lisi , Robert Foss , dri-devel@lists.freedesktop.org, NXP Linux Team , linux-amarula , linux-arm-kernel@lists.infradead.org, Jagan Teki Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Samsung MIPI DSIM master can also be found in i.MX8M Mini/Nano SoC. Add compatible and associated driver_data for it. Reviewed-by: Marek Vasut Reviewed-by: Frieder Schrempf Acked-by: Robert Foss Reviewed-by: Laurent Pinchart Signed-off-by: Marek Szyprowski Signed-off-by: Jagan Teki --- Changes for v13: - none Changes for v12: - collect RB from Marek Changes for v11: - collect RB from Frieder - collect ACK from Robert Changes for v10, v9: - none Changed for v8: - fix and update the comment Changes for v7, v6: - none Changes for v3: - enable DSIM_QUIRK_FIXUP_SYNC_POL quirk Changes for v5: - [mszyprow] rebased and adjusted to the new driver initialization - drop quirk Changes for v4: - none Changes for v3: - enable DSIM_QUIRK_FIXUP_SYNC_POL quirk Changes for v2: - collect Laurent r-b Changes for v1: - none drivers/gpu/drm/bridge/samsung-dsim.c | 44 +++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index e0dac7aeab37..9c64a71d2ebd 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -376,6 +376,24 @@ static const unsigned int exynos5433_reg_values[] = { [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), }; +static const unsigned int imx8mm_dsim_reg_values[] = { + [RESET_TYPE] = DSIM_SWRST, + [PLL_TIMER] = 500, + [STOP_STATE_CNT] = 0xf, + [PHYCTRL_ULPS_EXIT] = 0, + [PHYCTRL_VREG_LP] = 0, + [PHYCTRL_SLEW_UP] = 0, + [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), + [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), + [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), + [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26), + [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), + [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), + [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08), + [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), + [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), +}; + static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { .reg_ofs = exynos_reg_ofs, .plltmr_reg = 0x50, @@ -437,6 +455,22 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { .reg_values = exynos5422_reg_values, }; +static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { + .reg_ofs = exynos5433_reg_ofs, + .plltmr_reg = 0xa0, + .has_clklane_stop = 1, + .num_clks = 2, + .max_freq = 2100, + .wait_for_reset = 0, + .num_bits_resol = 12, + /* + * Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus + * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c + */ + .pll_p_offset = 14, + .reg_values = imx8mm_dsim_reg_values, +}; + static const struct samsung_dsim_driver_data * samsung_dsim_types[DSIM_TYPE_COUNT] = { [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data, @@ -444,6 +478,7 @@ samsung_dsim_types[DSIM_TYPE_COUNT] = { [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data, [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data, [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data, + [DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data, }; static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h) @@ -1843,7 +1878,16 @@ const struct dev_pm_ops samsung_dsim_pm_ops = { }; EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops); +static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = { + .hw_type = DSIM_TYPE_IMX8MM, + .host_ops = &generic_dsim_host_ops, +}; + static const struct of_device_id samsung_dsim_of_match[] = { + { + .compatible = "fsl,imx8mm-mipi-dsim", + .data = &samsung_dsim_imx8mm_pdata, + }, { /* sentinel. */ } }; MODULE_DEVICE_TABLE(of, samsung_dsim_of_match);