From patchwork Wed Mar 29 01:59:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 13191832 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A60B1C6FD18 for ; Wed, 29 Mar 2023 01:59:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5249310E962; Wed, 29 Mar 2023 01:59:26 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id C958E10E9A4 for ; Wed, 29 Mar 2023 01:59:23 +0000 (UTC) X-UUID: 50dd4d38cdd511eda9a90f0bb45854f4-20230329 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=nZJQ7bNevf6rdzPFTCjXijMbR0sOjgzTTeehhWLckao=; b=fPhi+dQibHzLok91yEqdLJow52wlKXreDUGm/1hgPYKz6TdMloqa2DGjlvvibc//mebgG98ZxI0JZh4VuUvmwR47NyqzdVdFV3rHjiGqZDoMz+m1d+rXkQ/YzSCcMqYxR8wnTyvGDCsicVc/90aBTOJ8I3I8cRfVw2XxrX9BJk4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22, REQID:e30a113d-c418-4b2f-8429-121d6732fb8c, IP:0, U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.22, REQID:e30a113d-c418-4b2f-8429-121d6732fb8c, IP:0, URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:120426c, CLOUDID:1fecaab4-beed-4dfc-bd9c-e1b22fa6ccc4, B ulkID:230329095918UEWH0971,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-UUID: 50dd4d38cdd511eda9a90f0bb45854f4-20230329 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1127424689; Wed, 29 Mar 2023 09:59:18 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Wed, 29 Mar 2023 09:59:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Wed, 29 Mar 2023 09:59:17 +0800 From: Nancy.Lin To: Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Subject: [PATCH v2] drm/mediatek: Add ovl_adaptor get format function Date: Wed, 29 Mar 2023 09:59:16 +0800 Message-ID: <20230329015916.21684-1-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shawn.sung@mediatek.com, singo.chang@mediatek.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, "Nancy.Lin" , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add ovl_adaptor get_format and get_num_formats component function. The two functions are need for getting the supported format in mtk_plane_init(). Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 ++ .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 24 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++ 3 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 0d28b2e2069c..da2de17b84e9 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -124,6 +124,8 @@ void mtk_ovl_adaptor_start(struct device *dev); void mtk_ovl_adaptor_stop(struct device *dev); unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev); struct device *mtk_ovl_adaptor_dma_dev_get(struct device *dev); +const u32 *mtk_ovl_adaptor_get_formats(struct device *dev); +size_t mtk_ovl_adaptor_get_num_formats(struct device *dev); void mtk_rdma_bypass_shadow(struct device *dev); int mtk_rdma_clk_enable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c index 046217828ab3..b5d28c392c57 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -25,6 +25,20 @@ #define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920 #define MTK_OVL_ADAPTOR_LAYER_NUM 4 +static const u32 formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, +}; + enum mtk_ovl_adaptor_comp_type { OVL_ADAPTOR_TYPE_RDMA = 0, OVL_ADAPTOR_TYPE_MERGE, @@ -297,6 +311,16 @@ void mtk_ovl_adaptor_disable_vblank(struct device *dev) mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); } +const u32 *mtk_ovl_adaptor_get_formats(struct device *dev) +{ + return formats; +} + +size_t mtk_ovl_adaptor_get_num_formats(struct device *dev) +{ + return ARRAY_SIZE(formats); +} + void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex) { mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 1a0c4f7e352a..f114da4d36a9 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -410,6 +410,8 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = { .disconnect = mtk_ovl_adaptor_disconnect, .add = mtk_ovl_adaptor_add_comp, .remove = mtk_ovl_adaptor_remove_comp, + .get_formats = mtk_ovl_adaptor_get_formats, + .get_num_formats = mtk_ovl_adaptor_get_num_formats, }; static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {