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([2804:14c:485:4b69:1c2d:271:d34:84ea]) by smtp.gmail.com with ESMTPSA id v12-20020a4aad8c000000b0053b909a5229sm7223691oom.4.2023.03.29.07.42.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 07:42:48 -0700 (PDT) From: Fabio Estevam To: neil.armstrong@linaro.org Subject: [PATCH 2/2] drm/exynos: Implement support for DSI clock and data lane polarity swap Date: Wed, 29 Mar 2023 11:41:55 -0300 Message-Id: <20230329144155.699196-2-festevam@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230329144155.699196-1-festevam@gmail.com> References: <20230329144155.699196-1-festevam@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, devicetree@vger.kernel.org, Fabio Estevam , dri-devel@lists.freedesktop.org, robh+dt@kernel.org, jagan@amarulasolutions.com, krzysztof.kozlowski+dt@linaro.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Marek Vasut Implement support for DSI clock and data lane DN/DP polarity swap by means of decoding 'lane-polarities' DT property. The controller does support DN/DP swap of clock lane and all data lanes, the controller does not support polarity swap of individual data lane bundles, add a check which verifies all data lanes have the same polarity. This has been validated on an imx8mm board that actually has the MIPI DSI clock lanes inverted. Signed-off-by: Marek Vasut Signed-off-by: Fabio Estevam Reviewed-by: Jagan Teki --- drivers/gpu/drm/bridge/samsung-dsim.c | 27 ++++++++++++++++++++++++++- include/drm/bridge/samsung-dsim.h | 2 ++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index e0a402a85787..5791148e2da2 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -183,6 +183,8 @@ #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) /* DSIM_PLLCTRL */ +#define DSIM_PLL_DPDNSWAP_CLK (1 << 25) +#define DSIM_PLL_DPDNSWAP_DAT (1 << 24) #define DSIM_FREQ_BAND(x) ((x) << 24) #define DSIM_PLL_EN BIT(23) #define DSIM_PLL_P(x, offset) ((x) << (offset)) @@ -622,6 +624,11 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, reg |= DSIM_FREQ_BAND(band); } + if (dsi->swap_dn_dp_clk) + reg |= DSIM_PLL_DPDNSWAP_CLK; + if (dsi->swap_dn_dp_data) + reg |= DSIM_PLL_DPDNSWAP_DAT; + samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg); timeout = 1000; @@ -1696,7 +1703,9 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) { struct device *dev = dsi->dev; struct device_node *node = dev->of_node; - int ret; + u32 lane_polarities[5] = { 0 }; + struct device_node *endpoint; + int i, nr_lanes, ret; ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency", &dsi->pll_clk_rate); @@ -1713,6 +1722,22 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) if (ret < 0) return ret; + endpoint = of_graph_get_endpoint_by_regs(node, 1, -1); + nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); + if (nr_lanes > 0 && nr_lanes <= 4) { + /* Polarity 0 is clock lane, 1..4 are data lanes. */ + of_property_read_u32_array(endpoint, "lane-polarities", + lane_polarities, nr_lanes + 1); + for (i = 1; i <= nr_lanes; i++) { + if (lane_polarities[1] != lane_polarities[i]) + DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match"); + } + if (lane_polarities[0]) + dsi->swap_dn_dp_clk = true; + if (lane_polarities[1]) + dsi->swap_dn_dp_data = true; + } + return 0; } diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h index ba5484de2b30..6a37d1e079bf 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -95,6 +95,8 @@ struct samsung_dsim { u32 mode_flags; u32 format; + bool swap_dn_dp_clk; + bool swap_dn_dp_data; int state; struct drm_property *brightness; struct completion completed;