Message ID | 20230330104233.785097-2-festevam@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v2,1/2] dt-bindings: display: bridge: ldb: Add i.MX6SX support | expand |
On 30/03/2023 12:42, Fabio Estevam wrote: > From: Fabio Estevam <festevam@denx.de> > > i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout > with i.MX8MP and i.MX93. > > There is no LVDS CTRL register on the i.MX6SX, so only write to > this register on the appropriate SoCs. > > Add support for the i.MX6SX LDB. > > Tested on a imx6sx-sdb board with a Hannstar HSD100PXN1 LVDS panel > and also on a custom i.MX6SX-based board. > > Signed-off-by: Fabio Estevam <festevam@denx.de> > --- > Changes since v1: > - None > > drivers/gpu/drm/bridge/fsl-ldb.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c > index 450b352914f4..f8e5d8ab98e3 100644 > --- a/drivers/gpu/drm/bridge/fsl-ldb.c > +++ b/drivers/gpu/drm/bridge/fsl-ldb.c > @@ -56,6 +56,7 @@ > #define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17) > > enum fsl_ldb_devtype { > + IMX6SX_LDB, > IMX8MP_LDB, > IMX93_LDB, > }; > @@ -64,9 +65,14 @@ struct fsl_ldb_devdata { > u32 ldb_ctrl; > u32 lvds_ctrl; > bool lvds_en_bit; > + bool not_lvds_ctrl; > }; > > static const struct fsl_ldb_devdata fsl_ldb_devdata[] = { > + [IMX6SX_LDB] = { > + .ldb_ctrl = 0x18, > + .not_lvds_ctrl = true, > + }, > [IMX8MP_LDB] = { > .ldb_ctrl = 0x5c, > .lvds_ctrl = 0x128, > @@ -202,6 +208,9 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, > > regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg); > > + if (fsl_ldb->devdata->not_lvds_ctrl) > + return; > + > /* Program LVDS_CTRL */ > reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN | > LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN; > @@ -228,7 +237,8 @@ static void fsl_ldb_atomic_disable(struct drm_bridge *bridge, > regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, > LVDS_CTRL_LVDS_EN); > else > - regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0); > + if (!fsl_ldb->devdata->not_lvds_ctrl) > + regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0); > regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0); > > clk_disable_unprepare(fsl_ldb->clk); > @@ -355,6 +365,8 @@ static void fsl_ldb_remove(struct platform_device *pdev) > } > > static const struct of_device_id fsl_ldb_match[] = { > + { .compatible = "fsl,imx6sx-ldb", > + .data = &fsl_ldb_devdata[IMX6SX_LDB], }, > { .compatible = "fsl,imx8mp-ldb", > .data = &fsl_ldb_devdata[IMX8MP_LDB], }, > { .compatible = "fsl,imx93-ldb", Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On 3/30/23 12:42, Fabio Estevam wrote: > From: Fabio Estevam <festevam@denx.de> > > i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout > with i.MX8MP and i.MX93. > > There is no LVDS CTRL register on the i.MX6SX, so only write to > this register on the appropriate SoCs. > > Add support for the i.MX6SX LDB. > > Tested on a imx6sx-sdb board with a Hannstar HSD100PXN1 LVDS panel > and also on a custom i.MX6SX-based board. > > Signed-off-by: Fabio Estevam <festevam@denx.de> > --- > Changes since v1: > - None > > drivers/gpu/drm/bridge/fsl-ldb.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c > index 450b352914f4..f8e5d8ab98e3 100644 > --- a/drivers/gpu/drm/bridge/fsl-ldb.c > +++ b/drivers/gpu/drm/bridge/fsl-ldb.c > @@ -56,6 +56,7 @@ > #define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17) > > enum fsl_ldb_devtype { > + IMX6SX_LDB, > IMX8MP_LDB, > IMX93_LDB, > }; > @@ -64,9 +65,14 @@ struct fsl_ldb_devdata { > u32 ldb_ctrl; > u32 lvds_ctrl; > bool lvds_en_bit; > + bool not_lvds_ctrl; You might want to rename this one to something like "composite_control_reg" since the MX6SX only has one LDB control register instead of two like the newer SoCs. But that's optional change. Reviewed-by: Marek Vasut <marex@denx.de>
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c index 450b352914f4..f8e5d8ab98e3 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -56,6 +56,7 @@ #define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17) enum fsl_ldb_devtype { + IMX6SX_LDB, IMX8MP_LDB, IMX93_LDB, }; @@ -64,9 +65,14 @@ struct fsl_ldb_devdata { u32 ldb_ctrl; u32 lvds_ctrl; bool lvds_en_bit; + bool not_lvds_ctrl; }; static const struct fsl_ldb_devdata fsl_ldb_devdata[] = { + [IMX6SX_LDB] = { + .ldb_ctrl = 0x18, + .not_lvds_ctrl = true, + }, [IMX8MP_LDB] = { .ldb_ctrl = 0x5c, .lvds_ctrl = 0x128, @@ -202,6 +208,9 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg); + if (fsl_ldb->devdata->not_lvds_ctrl) + return; + /* Program LVDS_CTRL */ reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN | LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN; @@ -228,7 +237,8 @@ static void fsl_ldb_atomic_disable(struct drm_bridge *bridge, regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, LVDS_CTRL_LVDS_EN); else - regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0); + if (!fsl_ldb->devdata->not_lvds_ctrl) + regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0); regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0); clk_disable_unprepare(fsl_ldb->clk); @@ -355,6 +365,8 @@ static void fsl_ldb_remove(struct platform_device *pdev) } static const struct of_device_id fsl_ldb_match[] = { + { .compatible = "fsl,imx6sx-ldb", + .data = &fsl_ldb_devdata[IMX6SX_LDB], }, { .compatible = "fsl,imx8mp-ldb", .data = &fsl_ldb_devdata[IMX8MP_LDB], }, { .compatible = "fsl,imx93-ldb",