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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id n7-20020a2e7207000000b002986854f27dsm134573ljc.23.2023.03.30.18.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 18:14:58 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 03:14:50 +0200 Subject: [PATCH v3 2/5] drm/msm/a6xx: Add support for A650 speed binning MIME-Version: 1.0 Message-Id: <20230331-topic-konahana_speedbin-v3-2-2dede22dd7f7@linaro.org> References: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> In-Reply-To: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680225294; l=1412; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=42U2yCRDQAALlywjy8FiLoqbAeo9f7qbW4rrzl+BgmY=; b=dwyPUzW5kyB7cpYIsra0jqgoc9iICEbp333fN21/hW1uI9eAgh9lyZx3qLIhTqeBJe7Uf2/WSJLw 8UXuc7NcD4q+iFYH51Ld8y73WVcYc3NMkKeHz0Kfjv8gbc3apCoK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Konrad Dybcio , Marijn Suijten , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for matching QFPROM fuse values to get the correct speed bin on A650 (SM8250) GPUs. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 663090973c1b..2afc160cf06a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1900,6 +1900,21 @@ static u32 a640_get_speed_bin(u32 fuse) return UINT_MAX; } +static u32 a650_get_speed_bin(u32 fuse) +{ + if (fuse == 0) + return 0; + else if (fuse == 1) + return 1; + /* Yep, 2 and 3 are swapped! :/ */ + else if (fuse == 2) + return 3; + else if (fuse == 3) + return 2; + + return UINT_MAX; +} + static u32 adreno_7c3_get_speed_bin(u32 fuse) { if (fuse == 0) @@ -1928,6 +1943,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) val = a640_get_speed_bin(fuse); + if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + val = a650_get_speed_bin(fuse); + if (val == UINT_MAX) { DRM_DEV_ERROR(dev, "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",