From patchwork Wed Apr 19 18:09:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yang, Fei" X-Patchwork-Id: 13217234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E5C4C77B7A for ; Wed, 19 Apr 2023 18:08:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E051C10EA7B; Wed, 19 Apr 2023 18:08:35 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id B51B110EA4D; Wed, 19 Apr 2023 18:08:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681927711; x=1713463711; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BzTAXktiDA3Vcy8Spwptuee23n+AvXz48+tgBh4dA+o=; b=iICgTUk0UWgUe2h4SqM322V0OL8B7CRZ2unCigVfwLaRZAiJuSqi0PW7 zzMp8mEh2Y5gr5WeHHbjMIvuF90MlVK5QT75/Z0e8JiZrR0ngpJ6CMltL r67jUGcjQN6iFp9G+M5ex/HArwoUQHaVN9GT7m9/9uwDwWTmBVihGfxVh 9jJ8lP2ShkARAL0F+50Rqx5lpWgBZYqBhcTRQJ9jki8VZ5z2Zwwtku6wX v2SFf5Wlij6HmwWHIxHBaHWKom4fCdaKy663GAXCSfz2gwX3MDBRKfBtz pk7EY0LI31jMO38g4sJJrOyk0oS+h4sJg717L8YR7bbwa08e7FA8Goaag Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10685"; a="329695025" X-IronPort-AV: E=Sophos;i="5.99,208,1677571200"; d="scan'208";a="329695025" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2023 11:08:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10685"; a="724139437" X-IronPort-AV: E=Sophos;i="5.99,208,1677571200"; d="scan'208";a="724139437" Received: from fyang16-desk.jf.intel.com ([10.24.96.243]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2023 11:08:29 -0700 From: fei.yang@intel.com To: intel-gfx@lists.freedesktop.org Subject: [PATCH 5/8] drm/i915/mtl: end support for set caching ioctl Date: Wed, 19 Apr 2023 11:09:39 -0700 Message-Id: <20230419180942.2494156-6-fei.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419180942.2494156-1-fei.yang@intel.com> References: <20230419180942.2494156-1-fei.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fei Yang , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Fei Yang The design is to keep Buffer Object's caching policy immutable through out its life cycle. This patch ends the support for set caching ioctl from MTL onward. While doing that we also set BO's to be 1-way coherent at creation time because GPU is no longer automatically snooping CPU cache. For UMD's need to fine tune the caching policy for BO's, a follow up patch will extend the GEM_CREATE uAPI to allow UMD's specify caching mode at BO creation time. Signed-off-by: Fei Yang --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++ drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 9 ++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index d2d5a24301b2..bb3575b1479f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -337,6 +337,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, if (IS_DGFX(i915)) return -ENODEV; + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) + return -EOPNOTSUPP; + switch (args->caching) { case I915_CACHING_NONE: level = I915_CACHE_NONE; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c index 37d1efcd3ca6..cad4a6017f4b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c @@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region *mem, obj->write_domain = I915_GEM_DOMAIN_CPU; obj->read_domains = I915_GEM_DOMAIN_CPU; - if (HAS_LLC(i915)) + /* + * MTL doesn't snoop CPU cache by default for GPU access (namely + * 1-way coherency). However some UMD's are currently depending on + * that. Make 1-way coherent the default setting for MTL. A follow + * up patch will extend the GEM_CREATE uAPI to allow UMD's specify + * caching mode at BO creation time + */ + if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))) /* On some devices, we can have the GPU use the LLC (the CPU * cache) for about a 10% performance improvement * compared to uncached. Graphics requests other than