From patchwork Wed Apr 19 23:00:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yang, Fei" X-Patchwork-Id: 13217634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD63FC77B7E for ; Wed, 19 Apr 2023 23:00:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DA59110E25A; Wed, 19 Apr 2023 23:00:00 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 932D610EB38; Wed, 19 Apr 2023 22:59:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681945186; x=1713481186; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=95RJJVu6hdvALpeZ3Qj5fWgHQaswgjOgutOBhErMrS0=; b=Gcp3BfP/bpFPD1olcSoHCnCYaBAQwKFcpWJpyqI2WWFhEWJr7xBJ4uXn SDx9VTB5P2OM0EWM7+XWERDhY1Ur8+6QN/NzUPdWQm9MPQDbmW+6wVf3o OeZwQlmIuWuKp0fnWN+Fs2bnAZYPOBp/dUSKhXebK/HTounOFnwnJL3f3 /4eau/Z2JLZWnXgCNP8IiMSsd6te2sEmc4iUaBqaJeiSp60cYkue6EKaH EJzV6mDrt85QlLUfuusfpgH0iof0Z+/Q3RI4dqgahJzwNoZ/83YEAyp0l NxcyCYBAUfN0uvD8dwdJwT4Kq+1Nvrd32+mgb4rgln4Q+YnFJLeZbaiuf g==; X-IronPort-AV: E=McAfee;i="6600,9927,10685"; a="431858537" X-IronPort-AV: E=Sophos;i="5.99,210,1677571200"; d="scan'208";a="431858537" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2023 15:59:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10685"; a="815787135" X-IronPort-AV: E=Sophos;i="5.99,210,1677571200"; d="scan'208";a="815787135" Received: from fyang16-desk.jf.intel.com ([10.24.96.243]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2023 15:59:46 -0700 From: fei.yang@intel.com To: intel-gfx@lists.freedesktop.org Subject: [PATCH 5/8] drm/i915/mtl: end support for set caching ioctl Date: Wed, 19 Apr 2023 16:00:55 -0700 Message-Id: <20230419230058.2659455-6-fei.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419230058.2659455-1-fei.yang@intel.com> References: <20230419230058.2659455-1-fei.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrzej Hajda , Fei Yang , dri-devel@lists.freedesktop.org, Andi Shyti Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Fei Yang The design is to keep Buffer Object's caching policy immutable through out its life cycle. This patch ends the support for set caching ioctl from MTL onward. While doing that we also set BO's to be 1-way coherent at creation time because GPU is no longer automatically snooping CPU cache. For UMD's need to fine tune the caching policy for BO's, a follow up patch will extend the GEM_CREATE uAPI to allow UMD's specify caching mode at BO creation time. Signed-off-by: Fei Yang Reviewed-by: Andi Shyti Reviewed-by: Andrzej Hajda --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++ drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 9 ++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index d2d5a24301b2..bb3575b1479f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -337,6 +337,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, if (IS_DGFX(i915)) return -ENODEV; + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) + return -EOPNOTSUPP; + switch (args->caching) { case I915_CACHING_NONE: level = I915_CACHE_NONE; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c index 37d1efcd3ca6..cad4a6017f4b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c @@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region *mem, obj->write_domain = I915_GEM_DOMAIN_CPU; obj->read_domains = I915_GEM_DOMAIN_CPU; - if (HAS_LLC(i915)) + /* + * MTL doesn't snoop CPU cache by default for GPU access (namely + * 1-way coherency). However some UMD's are currently depending on + * that. Make 1-way coherent the default setting for MTL. A follow + * up patch will extend the GEM_CREATE uAPI to allow UMD's specify + * caching mode at BO creation time + */ + if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))) /* On some devices, we can have the GPU use the LLC (the CPU * cache) for about a 10% performance improvement * compared to uncached. Graphics requests other than