From patchwork Tue May 2 04:15:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yang, Fei" X-Patchwork-Id: 13228480 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB8A3C77B73 for ; Tue, 2 May 2023 04:14:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5C05110E402; Tue, 2 May 2023 04:14:28 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 464C610E400; Tue, 2 May 2023 04:14:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683000867; x=1714536867; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8/YvCM5RTKuWJ7FLn0hu+1tlU1aJdfiJBm3nqlmN+4M=; b=cELvCmvYiDD+yHMRmi5UL7zFOm23KZUl1WFIV89+7T3PLj8nH+zlZGZz mLEjZgm+T+Ha062yVHoHPOhRnYYKy9FfCVwyZhBLBgELgrL+ylKwPfyWA 226J+JoO9AiWjfC8MFn/BeK0VxGbqL2qLc6cpBS5mPW2SqCLRMF8j2Xvu GcIuF0fzcxlk1JPwTO0sidPCiJO1Ev9QYPchDkaWHBsP6BsFitcw4wyMI in87FQKRvy8gAkBDyHW70lCOCw7A/UCzmJzn6tkAKknt7i2J7Qhb94aIr TpnZeiO1zsEr3ZOUm4jE5tMlySyE5CtT/meBwIdZAJUTsX8Qc0F3Rc5w4 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10697"; a="347116761" X-IronPort-AV: E=Sophos;i="5.99,243,1677571200"; d="scan'208";a="347116761" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 May 2023 21:14:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10697"; a="726593806" X-IronPort-AV: E=Sophos;i="5.99,243,1677571200"; d="scan'208";a="726593806" Received: from fyang16-desk.jf.intel.com ([10.24.96.243]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 May 2023 21:14:25 -0700 From: fei.yang@intel.com To: intel-gfx@lists.freedesktop.org Subject: [PATCH v4 4/5] drm/i915/mtl: end support for set caching ioctl Date: Mon, 1 May 2023 21:15:25 -0700 Message-Id: <20230502041526.2170497-5-fei.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230502041526.2170497-1-fei.yang@intel.com> References: <20230502041526.2170497-1-fei.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrzej Hajda , Fei Yang , dri-devel@lists.freedesktop.org, Andi Shyti Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Fei Yang The design is to keep Buffer Object's caching policy immutable through out its life cycle. This patch ends the support for set caching ioctl from MTL onward. While doing that we also set BO's to be 1-way coherent at creation time because GPU is no longer automatically snooping CPU cache. For userspace components needing to fine tune the caching policy for BO's, a follow up patch will extend the GEM_CREATE uAPI to allow them specify caching mode at BO creation time. Signed-off-by: Fei Yang Reviewed-by: Andi Shyti Reviewed-by: Andrzej Hajda --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++ drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 9 ++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 95a0d845d949..e62db612aea6 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -338,6 +338,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, if (IS_DGFX(i915)) return -ENODEV; + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) + return -EOPNOTSUPP; + switch (args->caching) { case I915_CACHING_NONE: level = I915_CACHE_NONE; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c index 37d1efcd3ca6..cad4a6017f4b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c @@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region *mem, obj->write_domain = I915_GEM_DOMAIN_CPU; obj->read_domains = I915_GEM_DOMAIN_CPU; - if (HAS_LLC(i915)) + /* + * MTL doesn't snoop CPU cache by default for GPU access (namely + * 1-way coherency). However some UMD's are currently depending on + * that. Make 1-way coherent the default setting for MTL. A follow + * up patch will extend the GEM_CREATE uAPI to allow UMD's specify + * caching mode at BO creation time + */ + if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))) /* On some devices, we can have the GPU use the LLC (the CPU * cache) for about a 10% performance improvement * compared to uncached. Graphics requests other than