From patchwork Tue May 2 08:16:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13228580 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7DA6BC7EE24 for ; Tue, 2 May 2023 08:17:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2EFBC10E4BC; Tue, 2 May 2023 08:17:15 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by gabe.freedesktop.org (Postfix) with ESMTPS id 16F5110E4BC for ; Tue, 2 May 2023 08:17:13 +0000 (UTC) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:c5f8:7372:f042:90a2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1AA6E6605636; Tue, 2 May 2023 09:17:06 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1683015426; bh=e+z2Zo2svQXmXgzmCCJ1yKre7NYLgaysXM+EwLcVdPw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g7exdU/lMDKFOa/Aq8YbHIXa4raSyWn4Z0d7cM5qHt1CrxDg49fvp6FBX0TYFsGQA 8PQOUDcCh2T/g710+OxvDkfWq7WDdCOcoI1kSG70rjsJfWN3VFn/vbzIDaQ7fPyZP2 tpbN+y+pLvYZJt5eWIoOn5e5FVWQI6r/zecfwNhI6NWReml0B71h8F/XXeVIExOiM4 ls1j1oblXdcE2e6A7oXdNPcex6/CyO/A6tpWYgP/Tjvdz+8ybqSEU1j/rlmjqWRpRF BuwteCJvytLLCtlbLWOocFSfrbJ6crVVowOMfbtsTASRTR+t4LI0sTv+IFvO1OrOvU MOZIVkd1OFhLQ== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Subject: [PATCH 11/11] drm/mediatek: gamma: Program gamma LUT type for descending or rising Date: Tue, 2 May 2023 10:16:50 +0200 Message-Id: <20230502081650.25947-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230502081650.25947-1-angelogioacchino.delregno@collabora.com> References: <20230502081650.25947-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, wenst@chromium.org, matthias.bgg@gmail.com, kernel@collabora.com, linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" All of the SoCs that don't have dithering control in the gamma IP have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is "descending" (bit set) or "rising" (bit cleared): make sure to set it correctly after programming the LUT. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 3501c8b549be..ac7ab3863f6f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -22,6 +22,7 @@ #define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) +#define GAMMA_LUT_TYPE BIT(2) #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) @@ -88,6 +89,16 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return lut_size; } +static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut_size) +{ + u64 first, last; + + first = lut[0].red + lut[0].green + lut[0].blue; + last = lut[lut_size].red + lut[lut_size].green + lut[lut_size].blue; + + return !!(first > last); +} + void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); @@ -181,6 +192,14 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt } } + if (gamma && !gamma->data->has_dither) { + /* Descending or Rising LUT */ + if (mtk_gamma_lut_is_descending(lut, lut_size)) + cfg_val |= FIELD_PREP(GAMMA_LUT_TYPE, 1); + else + cfg_val &= ~GAMMA_LUT_TYPE; + } + /* Enable the gamma table */ cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1);