From patchwork Sat May 6 19:24:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13233605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3FC3C77B7F for ; Sat, 6 May 2023 19:25:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 18A2C10E0EB; Sat, 6 May 2023 19:25:35 +0000 (UTC) Received: from mail-io1-xd2a.google.com (mail-io1-xd2a.google.com [IPv6:2607:f8b0:4864:20::d2a]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0448910E0E5 for ; Sat, 6 May 2023 19:25:29 +0000 (UTC) Received: by mail-io1-xd2a.google.com with SMTP id ca18e2360f4ac-763da065494so65454939f.0 for ; Sat, 06 May 2023 12:25:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683401129; x=1685993129; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F+jdPRHPNZecxppiqvpxaH4jO4aRXCVPuKLqtE0Zolk=; b=ChfCBtxl2QqV4MVQGPRqPVuqZd5rQiNo/V6xQY7jf09NctjLRvG335IEKcl5mhwvKE Gs1fS3j+XoxB1eQpFGadYrdqo1Lseg8z7qUY/6PL6MdaR4DZqb/VHHHVMvsHGMrOsZP5 hwhopotDnqenbQobyRM8txddusrE9qYdVfzB3Begy337ORRxXzgSw7LgE19gWYPc0UXV OZESW/51WX/wl9m2HWDS9F0aaMyq5t9OLf/2ASOto4qdETfthcGLvqTlf6ujNcq2382e tlKPyb51ygp+qkpsslzbkr1i4M3YYKAAzXEfWzxIwxmSxZg183+kkiWAysTnP48wEgjB hEvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683401129; x=1685993129; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F+jdPRHPNZecxppiqvpxaH4jO4aRXCVPuKLqtE0Zolk=; b=OuCzQEEuomXW9iDBV72OWMeU/BiTcdFIjhv7Xkp+DZtjEgu/Dth9t1f9eMDkmM5U8n N042JM7TuBDr7Th8gnLSIp9WDfVS3fpuOK/On6W9GBxZ845UQrgjzluN27K3T2gFrV2Z FeCdfl4XiFwgxPrFdylOjrrngYpqVLMks6NytPObIlwCJCdRfsGQHM9DljlbuJfOwZD8 FkAlTdR3TCIMAkFYmK+2uGPveiGv/BQuvJIwAejsvIOoWBScKuGKJyvnsB5KaQMKH7xo /GrJByKeLcZfuNg3PFBx01hcqkSYHHIgGI+bRHK95ja8iwwOhd8N5oqDffngcwGxcolv apSg== X-Gm-Message-State: AC+VfDx71rMVyRWyz7DL2gz2oo1o17ypemVvcqtGAG9GmFXk2ZdARWpb h+PB0OxHvZCIDypYGriUnmJoePqSOhH8kA== X-Google-Smtp-Source: ACHHUZ6MOewNncTk3Cc+Mw4Hxz+pNDQGCvS+oc4Dnx/JSrwAXMcBYBoCtn1pEyNJscQ0VP2IuqryeQ== X-Received: by 2002:a5e:dd05:0:b0:766:41fa:e26f with SMTP id t5-20020a5edd05000000b0076641fae26fmr3518860iop.10.1683401128704; Sat, 06 May 2023 12:25:28 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:5e49:1bed:79d0:5c25]) by smtp.gmail.com with ESMTPSA id z18-20020a05663822b200b0041631393ac9sm847824jas.18.2023.05.06.12.25.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 12:25:28 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Subject: [PATCH V5 6/6] drm: bridge: samsung-dsim: Support non-burst mode Date: Sat, 6 May 2023 14:24:53 -0500 Message-Id: <20230506192453.725621-7-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230506192453.725621-1-aford173@gmail.com> References: <20230506192453.725621-1-aford173@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , Jernej Skrabec , Robert Foss , Jonas Karlman , aford@beaconembedded.com, Frieder Schrempf , linux-kernel@vger.kernel.org, Laurent Pinchart , Andrzej Hajda , Chen-Yu Tsai , Marek Szyprowski , Adam Ford , Jagan Teki Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The high-speed clock is hard-coded to the burst-clock frequency specified in the device tree. However, when using devices like certain bridge chips without burst mode and varying resolutions and refresh rates, it may be necessary to set the high-speed clock dynamically based on the desired pixel clock for the connected device. This also removes the need to set a clock speed from the device tree for non-burst mode operation, since the pixel clock rate is the rate requested from the attached device like a bridge chip. This should have no impact for people using burst-mode and setting the burst clock rate is still required for those users. If the burst clock is not present, change the error message to dev_info indicating the clock use the pixel clock. Lastly, cache the clock rate configured from samsung_dsim_set_pll in order to properly calculate the blanking regardless of whether or not the burst clock is set. Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf --- drivers/gpu/drm/bridge/samsung-dsim.c | 27 +++++++++++++++++++++------ include/drm/bridge/samsung-dsim.h | 1 + 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index d19a5c87b749..97872ffb903d 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -654,16 +654,28 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, reg = samsung_dsim_read(dsi, DSIM_STATUS_REG); } while ((reg & DSIM_PLL_STABLE) == 0); + dsi->hs_clock = fout; + return fout; } static int samsung_dsim_enable_clock(struct samsung_dsim *dsi) { - unsigned long hs_clk, byte_clk, esc_clk; + unsigned long hs_clk, byte_clk, esc_clk, pix_clk; unsigned long esc_div; u32 reg; + struct drm_display_mode *m = &dsi->mode; + int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + + /* m->clock is in KHz */ + pix_clk = m->clock * 1000; + + /* Use burst_clk_rate if available, otherwise use the pix_clk */ + if (dsi->burst_clk_rate) + hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); + else + hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes)); - hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); if (!hs_clk) { dev_err(dsi->dev, "failed to configure DSI PLL\n"); return -EFAULT; @@ -952,7 +964,7 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) u32 reg; if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { - int byte_clk_khz = dsi->burst_clk_rate / 1000 / 8; + int byte_clk_khz = dsi->hs_clock / 1000 / 8; int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; @@ -1802,10 +1814,13 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) return PTR_ERR(pll_clk); } + /* If it doesn't exist, use pixel clock instead of failing */ ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", - &dsi->burst_clk_rate, 0); - if (ret < 0) - return ret; + &dsi->burst_clk_rate, 1); + if (ret < 0) { + dev_info(dev, "Using pixel clock for HS clock frequency\n"); + dsi->burst_clk_rate = 0; + } ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", &dsi->esc_clk_rate, 0); diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h index 76ea8a1720cc..14176e6e9040 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -94,6 +94,7 @@ struct samsung_dsim { u32 pll_clk_rate; u32 burst_clk_rate; + u32 hs_clock; u32 esc_clk_rate; u32 lanes; u32 mode_flags;