| Message ID | 20230514184240.6184-1-juhapekka.heikkila@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers | expand |
On Sun, 14 May 2023, Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> wrote: > Add Tile4 type ccs modifiers with aux buffer needed for MTL > > Bspec: 49251, 49252, 49253 > Cc: dri-devel@lists.freedesktop.org > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> > Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Thanks for the patches and review. Pushed via drm-intel-next with Thomas' IRC ack. BR, Jani. > --- > include/uapi/drm/drm_fourcc.h | 43 +++++++++++++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > index de703c6be969..8db7fd3f743e 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -657,6 +657,49 @@ extern "C" { > */ > #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) > > +/* > + * Intel Color Control Surfaces (CCS) for display ver. 14 render compression. > + * > + * The main surface is tile4 and at plane index 0, the CCS is linear and > + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in > + * main surface. In other words, 4 bits in CCS map to a main surface cache > + * line pair. The main surface pitch is required to be a multiple of four > + * tile4 widths. > + */ > +#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13) > + > +/* > + * Intel Color Control Surfaces (CCS) for display ver. 14 media compression > + * > + * The main surface is tile4 and at plane index 0, the CCS is linear and > + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in > + * main surface. In other words, 4 bits in CCS map to a main surface cache > + * line pair. The main surface pitch is required to be a multiple of four > + * tile4 widths. For semi-planar formats like NV12, CCS planes follow the > + * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, > + * planes 2 and 3 for the respective CCS. > + */ > +#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14) > + > +/* > + * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render > + * compression. > + * > + * The main surface is tile4 and is at plane index 0 whereas CCS is linear > + * and at index 1. The clear color is stored at index 2, and the pitch should > + * be ignored. The clear color structure is 256 bits. The first 128 bits > + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented > + * by 32 bits. The raw clear color is consumed by the 3d engine and generates > + * the converted clear color of size 64 bits. The first 32 bits store the Lower > + * Converted Clear Color value and the next 32 bits store the Higher Converted > + * Clear Color value when applicable. The Converted Clear Color values are > + * consumed by the DE. The last 64 bits are used to store Color Discard Enable > + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line > + * corresponds to an area of 4x1 tiles in the main surface. The main surface > + * pitch is required to be a multiple of 4 tile widths. > + */ > +#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) > + > /* > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > *
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index de703c6be969..8db7fd3f743e 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -657,6 +657,49 @@ extern "C" { */ #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) +/* + * Intel Color Control Surfaces (CCS) for display ver. 14 render compression. + * + * The main surface is tile4 and at plane index 0, the CCS is linear and + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in + * main surface. In other words, 4 bits in CCS map to a main surface cache + * line pair. The main surface pitch is required to be a multiple of four + * tile4 widths. + */ +#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13) + +/* + * Intel Color Control Surfaces (CCS) for display ver. 14 media compression + * + * The main surface is tile4 and at plane index 0, the CCS is linear and + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in + * main surface. In other words, 4 bits in CCS map to a main surface cache + * line pair. The main surface pitch is required to be a multiple of four + * tile4 widths. For semi-planar formats like NV12, CCS planes follow the + * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, + * planes 2 and 3 for the respective CCS. + */ +#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14) + +/* + * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render + * compression. + * + * The main surface is tile4 and is at plane index 0 whereas CCS is linear + * and at index 1. The clear color is stored at index 2, and the pitch should + * be ignored. The clear color structure is 256 bits. The first 128 bits + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented + * by 32 bits. The raw clear color is consumed by the 3d engine and generates + * the converted clear color of size 64 bits. The first 32 bits store the Lower + * Converted Clear Color value and the next 32 bits store the Higher Converted + * Clear Color value when applicable. The Converted Clear Color values are + * consumed by the DE. The last 64 bits are used to store Color Discard Enable + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line + * corresponds to an area of 4x1 tiles in the main surface. The main surface + * pitch is required to be a multiple of 4 tile widths. + */ +#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) + /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks *