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Mon, 15 May 2023 22:39:51 -0700 Received: from alan-new-dev.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Tue, 16 May 2023 00:39:50 -0500 From: Alan Liu To: Subject: [PATCH 2/7] drm/amd/display: Implement set/get functions for secure display ROI properties Date: Tue, 16 May 2023 13:39:26 +0800 Message-ID: <20230516053931.1700117-3-HaoPing.Liu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516053931.1700117-1-HaoPing.Liu@amd.com> References: <20230516053931.1700117-1-HaoPing.Liu@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT053:EE_|IA1PR12MB8261:EE_ X-MS-Office365-Filtering-Correlation-Id: 40ba0eed-5ce2-4502-5ab0-08db55cff903 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GoFbMuIZnHmWNibZ9/qsUcBdK8Tm6zPf5IV/NTKgY4eAtDdhWSzCePlsHMEHWv4BEgB62NYWiMSxjqlctS57buYnMFyNgEyJNwDM7nJ3+v7KTuIjY1pGmXbp3yGtDKsKj6ubvXV1tVdzzOKOxxykW/VvTHQFA6RE5ox5c2NFhO5L3nQ10vu0ODLbGqDn13S9L2JmvyOZkyt8KkL9feQDZ9/gW7Anc6xS80YVaCHzjP5ThYX0RJDGjGezgULdiTLJxhrR113h0q+xfYBG/QKeFvcKfu+qbRtHYCceyNE9tK6Kd1ZekkBZgNa1ExuTEIxhjuP7r6c1Eba7c8HAdT7SzwfoLvwHDAe1lnMaCNfGt/RZWOmwk1stMCg6HnZKS3bGEJoLppQGK21VLqrI/GXbevwRFPkZJJO1DfL0xKmB9UeGigGok9PPo2MU+pHm1o7wtzD6gfUjLjchFHYnvo4UxTPevh6ERV0Uq1jH3ZzFbZ8Ol5cVhN+Eu26BxtBcVJaRMGcQlb6glNla03PF3TyGXHMw/XtiAY15hjxqcjkswQu/OIJud39S45HpG3Eu5qS8voH8FiEekb/WUYCm7xyPKvYNlx7ikAVRuvPmFA6A9ye6zZDxZGKtkfGea+OwU/Wi/ay8PzZy8EHu4vrxRCvur3e3QTKeKfHSpDxL2gLLf1pZbDaLMY42MwpC16O9tABNzv6KlGL7rWm8YNzRy2pL5xUTXYLRyrtCyzMWMOqYukhs2qlLaGXGZYKY5MTAwYubHE79CiEUNA59gLjE3MOM1A== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(346002)(39860400002)(136003)(396003)(376002)(451199021)(46966006)(36840700001)(40470700004)(86362001)(186003)(36860700001)(26005)(1076003)(6666004)(2616005)(47076005)(83380400001)(7696005)(82310400005)(336012)(426003)(8936002)(8676002)(478600001)(36756003)(2906002)(40460700003)(54906003)(5660300002)(81166007)(82740400003)(356005)(4326008)(41300700001)(6916009)(70206006)(70586007)(316002)(40480700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2023 05:39:52.5832 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40ba0eed-5ce2-4502-5ab0-08db55cff903 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8261 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alan Liu , wayne.lin@amd.com, lili.gong@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Implement set/get functions as the callback for userspace to update or get the secure display ROI configuration. Signed-off-by: Alan Liu --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 4af7ea6fbd65..e1a17f2d6f2d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -319,6 +319,53 @@ void amdgpu_dm_crtc_attach_secure_display_properties(struct amdgpu_device *adev, if (dm->secure_display_roi_property) drm_object_attach_property(&crtc->base, dm->secure_display_roi_property, 0); } + +static int amdgpu_dm_crtc_atomic_set_property(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state, + struct drm_property *property, + uint64_t val) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct dm_crtc_state *dm_state = to_dm_crtc_state(crtc_state); + + if (property == adev->dm.secure_display_roi_property) { + struct drm_property_blob *new_blob, **old_blob; + + old_blob = &dm_state->secure_display_state.roi_blob; + + if (val != 0) { + new_blob = drm_property_lookup_blob(dev, val); + if (!new_blob) + return -EINVAL; + } + dm_state->secure_display_state.roi_changed |= + drm_property_replace_blob(old_blob, new_blob); + + } else + return -EINVAL; + + return 0; +} + +static int amdgpu_dm_crtc_atomic_get_property(struct drm_crtc *crtc, + const struct drm_crtc_state *crtc_state, + struct drm_property *property, + uint64_t *val) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct dm_crtc_state *dm_state = to_dm_crtc_state(crtc_state); + + if (property == adev->dm.secure_display_roi_property) + *val = (dm_state->secure_display_state.roi_blob) + ? dm_state->secure_display_state.roi_blob->base.id : 0; + + else + return -EINVAL; + + return 0; +} #endif #ifdef CONFIG_DEBUG_FS @@ -348,6 +395,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { #if defined(CONFIG_DEBUG_FS) .late_register = amdgpu_dm_crtc_late_register, #endif +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY + .atomic_set_property = amdgpu_dm_crtc_atomic_set_property, + .atomic_get_property = amdgpu_dm_crtc_atomic_get_property, +#endif }; static void dm_crtc_helper_disable(struct drm_crtc *crtc)